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... of AC/ DC mode (Output inductance Lout of DC /AC mode): Lin = 6.74mH • Input capacitance of AC/ DC mode (Output capacitance Cout of DC /AC mode): Cin = 3.76uF • DC capacitor: Cdc = 600uF For AC/ DC. .. relationship omitted for AC/ DC operation This capacitor block will be added to standard cell if the cell works in DC /AC mode Hence, the following parameter for UPEC AC/ DC and DC /AC operation are adopted:... cell (UPEC) The philosophy of UPEC is to design standard cells, which can implement any of converter operation modes such as AC/ DC, AC/ AC, DC /AC and DC/ DC in single phase, paralleled phases and
Analysis and Design of Power Electronic Cell for Modular Power Electronic Systems: AC-DC Operation Niu Peng Ying A THESIS SUBMITTED FOR THE DEGREE OF MASTER OF ENGINEERING DEPARTMENT OF ELECTRICAL & COMPUTER ENGINEERING NATIONAL UNIVERSITY OF SINGAPORE 2004 i Acknowledgement The author would like to thank many people who have contributed to this work. Foremost among them is my research supervisor, Dr.Ashwin M Khambadkone and Prof. Oruganti, Ramesh, to whom I would like to record my sincere appreciation and gratitude for their valuable guidance and helpful suggestion. And also for his patience and helpfullness, which is most certainly valuable an deeply appreciated throughout the course of the work. Thanks to Mr Teo Thiam Teck, the lab technician of the Power Electronics Laboratory. Mr Teo had offered the author plenty of technical support and in many ways accelerated. Thanks to all of my labmates, for their concerned support and help me without reservation. Last, but not least, the author would like to thank all those who have helped her directly or indirectly in this project. ii Contents List of Figures viii 1 Introduction 1.1 The Concept of the Distributed Power Supply System(DPS) 1.2 The Concept of Universal Power Electronic Cell (UPEC) . . 1.3 Parts of Mode of UPEC . . . . . . . . . . . . . . . . . . . . 1.3.1 AC/DC operation . . . . . . . . . . . . . . . . . . . . 1.3.2 DC/AC operation . . . . . . . . . . . . . . . . . . . . 1.3.3 DC/DC operation . . . . . . . . . . . . . . . . . . . . 1.4 Scope of Thesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Literature Review 2.1 The Investigation in the PEBB Programs . . . . . . . . . . . . . 2.1.1 PEBB−A System Approach to Power Electronics . . . . 2.1.2 Hierarchical Architecture of Plug and Play PEBB system 2.1.3 Dataflow Architecture for PEBB . . . . . . . . . . . . . 2.1.4 Switching Technique . . . . . . . . . . . . . . . . . . . . 2.1.5 Interactions and Stability . . . . . . . . . . . . . . . . . 2.2 Operation Principle and Control Methods . . . . . . . . . . . . 2.2.1 The Basic UPEC Cell and AC/DC Operation . . . . . . 2.2.2 PI control . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.3 Deadbeat Control . . . . . . . . . . . . . . . . . . . . . . 2.3 Democratic current sharing control scheme . . . . . . . . . . . . 3 UPEC Cell and Parametric Selection 3.1 Selection of Parameters . . . . . . . . 3.1.1 Output Capacitor Selection . 3.1.2 Input Inductor Selection . . . 3.2 Circuit Implementation . . . . . . . . 3.2.1 Input Inductor Design . . . . 3.2.2 Semiconductor Circuit . . . . 3.2.3 Sensor and scaling . . . . . . 3.2.4 PCB consideration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1 4 5 6 6 7 8 . . . . . . . . . . . 10 10 10 12 15 16 18 19 19 21 22 23 . . . . . . . . 25 25 26 28 32 32 34 36 37 iii 3.2.5 3.2.6 3.2.7 Hardware Controller Implementation . . . . . . . . . . . . . . Problem of Output Voltage Ripple . . . . . . . . . . . . . . . Problem of Inrush Current . . . . . . . . . . . . . . . . . . . . 4 Closed loop control of UPEC using PI Controllers 4.1 Single Phase Close Loop Operation Using PI controllers . 4.1.1 Input current controller . . . . . . . . . . . . . . 4.1.2 Output Voltage Controller without Notch Filter . 4.1.3 Closed loop simulation results . . . . . . . . . . . 4.2 Output Voltage Controller with Notch Filter . . . . . . . 4.3 Analysis of the Power Factor . . . . . . . . . . . . . . . . 4.4 Controller Implementation . . . . . . . . . . . . . . . . . 4.4.1 Pulse-Width-Modulation . . . . . . . . . . . . . . 4.4.2 Natural and Regular Sampling . . . . . . . . . . . 4.5 Experimental Results for PI control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 43 44 46 46 47 49 51 54 56 58 59 64 66 . . . . . . . . . . 5 Closed Loop Control of UPEC using Deadbeat and Hysteresis Controllers 5.1 Single Phase Close Loop Operation Using deadbeat current controller 5.1.1 Design Constraints for Deadbeat Control . . . . . . . . . . . 5.1.2 Simulation Results . . . . . . . . . . . . . . . . . . . . . . . . 5.2 Experimental results . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2.1 The Performance of Deadbeat Control under Constraints . . 5.3 Hysteresis Current Controllers . . . . . . . . . . . . . . . . . . . . . . 72 72 75 78 80 82 83 6 Comparison of Controllers Performance 6.1 Comparison of Controllers Performance . . . . . . . . . . . . . . . . . 6.2 Parallel operation of two UPECs . . . . . . . . . . . . . . . . . . . . 86 86 88 7 Conclusion and Future Work 7.1 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.2 Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 92 94 Bibliography 96 A Circuit and Layout Scheme 103 iv Summary The need of low-cost, high-reliability, easy to use and maintain power electronic systems is fueling the drive for integration and standardization of modern electronic power supply. The development of power electronic block building (PEBB) meets these requirements. PEBB is a new paradigm in designing power electronic systems, it increases the power density and power power quality, user-friendly design, multifunctionality, and reliability. In this thesis, firstly I will provide review on the work of Power Electronic Block Building (PEBB), and then introduce the concept of Universal Power Electronic Cell (UPEC), a standard PEBB cell. In this context, a UPEC cell is defined as a half bridge converter, consisting of power semiconductors, the required passive components like inductors and capacitors and the driver electronics. The philosophy of UPEC cell is to design a standard PEBB cell, which is capable of implementing different kind of operation modes. This thesis studies the effect of input and output filter parameters on the respective performance criteria using simulation, then optimal parameters are chosen. Prototype hardware using the optimal parameters is established to test the control methods. v Among the various control strategies, for this work, two control schemes are employed for the AC/DC UPEC operation. One is the most popular, digital PI controller. Close loop digital PI controllers with and without output voltage filter are designed. Stability of the system is analyzed. And the performance is evaluated using simulation and experimental results. The experimental results reveal that the system performance can be improved with the output voltage filter. The other control scheme is deadbeat control. Simulation and experimental results demonstrate that deadbeat controller offers a fast dynamic response than PI controller. This thesis also studies the stability property and robustness problems of parameter mismatch for implementing deadbeat control. Comparison between PI current control and deadbeat current control is presented. Lastly, the thesis established democratic current sharing scheme for two paralleled non-identical UPECs, which guarantees averagely sharing the power current between two cells. vi Abbreviation and Symbols DPS MOSFET IGBT GTO BJT HVDC TCR PWM SPWM THD PF DPF UPEC PEBB CM NLC ADC CLC MSC ESL ESR EMI PCB PFC NTC DSP ISR Distributed Power Systems Metal-Oxide-Semiconductor Field Effect Transistors Insulated Gate Bipolar Transistor Gate Turn-off Thyristor Bipolar Junction Transistor High Voltage Direct Current Thrystor-Controlled Reactor Pulse Width Modulator Synchronous Pulse Width Modulator Total Harmonic Distortion Power Factor Displacement Power Factor Universal Power Electronic Cell Power Electronic Building Block Converter Module Nonlinear Carrier Control Analogue to Digital converter Current Limit Control Master Slave Control Equivalent Series Inductance Equivalent Series Resistance Electro Magnetic Interference Printed Circuit Board Power Factor Correction Negative Temperature Coefficient Digital Signal Processor Interrupt Service Routine vii Lin Cin Cout δV0 fnotch Ts KP W M ki ma mf Dn Input Inductor Input Capacitor Output Capacitor Output Voltage Ripple Notch Frequency Sampling Time PWM Gain Current Control Gain Amplitude Modulation Ratio Frequency Modulation Ratio Duty Ratio viii List of Figures 1.1 1.2 1.3 1.4 1.5 1.6 Power distribution from centralized power regulation . . Power distribution with distributed regulation . . . . . . Topology of basic UPEC cell . . . . . . . . . . . . . . . Topology of basic UPEC cell: AC/DC operation . . . . Topology of basic UPEC cell: DC/AC operation . . . . Topology of soft-switching UPEC cell: DC/DC operation . . . . . . 2 2 5 6 7 8 2.1 2.2 2.3 2.4 2.5 2.6 Dataflow graph of an open loop control algorithm for a PEBB based inverter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AC distribution power system . . . . . . . . . . . . . . . . . . . . . . Basic UPEC cell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . operation modes of UPEC . . . . . . . . . . . . . . . . . . . . . . . . Control diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block diagram of N parallel-connected converters under CLC scheme 16 18 19 20 21 24 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 Basic UPEC cell . . . . . . . . . . . . . . Cout -Lin -PF relationship at Cin =0.001uF . Cout -Lin -PF relationship at Cin =0.01uF . . Cout -Lin -PF relationship at Cin =0.1uF . . Lin -Cin -T HD relationship at Cout =1000uF Lin -Cin -T HD relationship at Cout =2000uF Lin -Cout -T HD relationship . . . . . . . . . The topology of the inductor core . . . . . Auxiliary driving circuit topology . . . . . Current sensor and scaling topology . . . . Hardware . . . . . . . . . . . . . . . . . . Inductive loop to be reduced . . . . . . . . DSP architecture . . . . . . . . . . . . . . Notch filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 27 28 29 30 30 31 33 36 37 38 39 42 44 4.1 4.2 4.3 Cascaded closed loop control . . . . . . . . . . . . . . . . . . . . . . . Block diagram of the current control loop . . . . . . . . . . . . . . . . Block diagram of the simplified current control loop . . . . . . . . . . 47 48 48 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ix 4.4 4.5 4.6 4.7 4.8 4.9 4.10 4.11 4.12 4.13 4.14 4.15 4.16 4.17 4.18 4.19 4.20 4.21 4.22 4.23 4.24 4.25 4.26 4.27 4.28 4.29 5.1 5.2 5.3 5.4 5.5 5.6 5.7 Bode plot of the current closed loop . . . . . . . . . . . . . . . . . . . Block diagram of the voltage control loop without notch filter . . . . Input current and voltage . . . . . . . . . . . . . . . . . . . . . . . . Output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output voltage under the load changing from 600W to 1200W . . . . Input current under the load changing from 600W to 1200W . . . . . Output voltage under the reference voltage changing from 600V to 650V Block diagram of the voltage control loop . . . . . . . . . . . . . . . . Block diagram of the simplified voltage control loop . . . . . . . . . . PF according to Formula . . . . . . . . . . . . . . . . . . . . . . . . DSP internal structure and sensing Interface Block Diagram for PI controllers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Main programming flow chart . . . . . . . . . . . . . . . . . . . . . . Interrupt program flow chart . . . . . . . . . . . . . . . . . . . . . . . Asymmetric and symmetric PWM signals . . . . . . . . . . . . . . . Symmetric PWM scheme . . . . . . . . . . . . . . . . . . . . . . . . . Harmonics spectrum . . . . . . . . . . . . . . . . . . . . . . . . . . . Uniform sampling topology . . . . . . . . . . . . . . . . . . . . . . . . Experimental results of input voltage and input current when no switches action . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Experimental results of output voltage when no switches action . . . Experimental results of input current at startup . . . . . . . . . . . . Voltage across IGBT when turn off . . . . . . . . . . . . . . . . . . . Experimental results of input voltage and input current with notch filter at 5kHz switching frequency . . . . . . . . . . . . . . . . . . . . Experimental results of input current without notch filter at 5kHz switching frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . Experimental result of input current with notch filter at 10kHz switching frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Experimental result of input current without notch filter at 10kHz switching frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . Experimental result of output voltage . . . . . . . . . . . . . . . . . . Operation states of UPEC . . . . . . . . . . . . . . . . . . . . . . . . Deadbeat current control diagram . . . . . . . . . . . . . . . . . . . . Trailing edge modulation . . . . . . . . . . . . . . . . . . . . . . . . . Deadbeat control under trailing edge modulation . . . . . . . . . . . relationship between ∆i and ∆v . . . . . . . . . . . . . . . . . . . . Output voltage control loop . . . . . . . . . . . . . . . . . . . . . . . Input current response under the input current reference from 5.21A to 10.42A for deadbeat current controller . . . . . . . . . . . . . . . . 5.8 Output voltage response under the output voltage reference changed from 600V to 650V . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.9 Input voltage and input current at switching frequency 20kHz . . . . 5.10 Input current at switching frequency 10kHz . . . . . . . . . . . . . . 50 50 52 52 53 53 54 55 55 58 59 60 61 62 63 64 65 67 67 68 68 69 69 70 70 71 73 74 75 76 78 79 79 79 80 81 x 5.11 5.12 5.13 5.14 5.15 Output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . Duty cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Hysteresis current control scheme . . . . . . . . . . . . . . . . . Input current response with hysteresis current control scheme . Output voltage response with hysteresis current control scheme . . . . . 81 81 84 84 85 6.1 6.2 6.3 Topology of control method . . . . . . . . . . . . . . . . . . . . . . . Input currents of two identical UPECs . . . . . . . . . . . . . . . . . Input currents of power supply and two identical UPECs under load change from 1000 watt to 1600 watt . . . . . . . . . . . . . . . . . . . Input currents of power supply and two nonidentical UPECs . . . . . Input currents of power supply and two nonidentical UPECs under load change from 1000 watt to 1600 watt . . . . . . . . . . . . . . . 89 90 91 AC/DC/AC operation topology . . . . . . . . . . . . . . . . . . . . . 94 6.4 6.5 7.1 . . . . . . . . . . 90 91 1 Chapter 1 Introduction Power supplies for the industry are becoming more and more important in our society. The greatest concern is power supply availability and redundancy. Not just because downtime can cause millions of dollars of loss in revenue for large corporations such as banks, insurance companies and e-business companies [1], but also because it is intolerable for mission-critical applications in which systems handle real-time commands and human lives. Thus, power electronics and related power processing technologies are called enabling infrastructure technology. Many such systems can be built using power electronic building blocks (PEBB). Different architectures are used to build these systems. 1.1 The Concept of the Distributed Power Supply System(DPS) Power within a system may be distributed in several ways. One configuration is the centralized supply that delivers filtered DC power via power conductors to circuits, 2 Distributed resistance within cable +Sense AC input Regulated DC Power input Converter Load1 Load2 Loadn -Sense Figure 1.1: Power distribution from centralized power regulation Distributed resistance within cable + AC input Unregulated Power Converter Local Regulated Load1 converter Local Regulated converter Load2 Local Regulated converter Loadn _ Figure 1.2: Power distribution with distributed regulation sensors, and actuators. Another configuration is the distributed supply that delivers raw, unfiltered DC power to local regulation units. Fig.1.1 illustrates a centralized supply, and Fig.1.2 shows a distributed supply. Centralized power system may use either a linear or switching power supply. Typically, it delivers low voltage, sometimes at moderate amounts of current. It is simple in concept and relies on low-impedance conductors to distribute the current to the circuits and components. Centralized distribution is best suited for small, localized systems; these range from small handheld devices and personal computers to 21-slot 3 backplanes in equipment chassis. Distributed power systems(DPS) have multiple points of power conversion. They can distribute higher voltages at lower currents, than centralized supplies, to local power converters, which usually are switching power supplies. They do not need heavy, expensive conductors. Distributed systems are best suited for big systems such as large equipment racks, aircraft, and ships. They tend to be more robust than centralized supplies because they can isolate failure. If designed carefully, they can be simpler to maintain and repair. The requirements of low-cost, high-reliability, easy to use power processing system in power electronic industry is becoming more and more pronounced. The wide use of DPS has given power supply industry the opportunity to develop a standardized modular approach to power processing. The DPS architecture can better address the increasing concerns regarding fault tolerance, improved reliability, service ability and redundancy without a significant added cost. The main requirements to put on a distributed power system are listed below. • The power system should be well adapted to operate with existing sources and loads, in terms of voltage and frequency. It should also provide a high degree of load and source power controllability. • The system should be easily expandable, ie., it should be possible to add, without altering already connected units. • Communication between individual converters should be avoided since addition of new units will complicate the interconnections. Also, the system would 4 suffer from reliability problems. On the other hand, communication at a low bandwidth is considered necessary for supervisory control. Therefore, single converters are allowed to rely on low bandwidth communication but should be able to operate as stand-alone units. • The degree of personal safety should be equal to or better than in the present power system. 1.2 The Concept of Universal Power Electronic Cell (UPEC) PEBB is a new paradigm of system design. The traditional power processing units are mostly DC/DC PWM switching converters. With the introduction of the DPS, developing an integrated system approach to standard power electronic elements with packaging techniques becomes relevant. One way to realize this approach is by using power electronics building blocks (PEBB) concept. PEBB, a concept proposed by the Office of Naval Research (ONR)[2], essentially involves the integration of large-scale power electronics systems using standardized building blocks. The goal of the PEBB development is to create a power processing component that moves most of the design away from specific circuit topology considerations and power electronic switches and associated inductors, capacitors and other ancillary components selection, up to a systems level. PEBBs are not limited to being solely the building blocks of the converter power stage. A PEBB can be a standard control building block or even a standard converter. The major advantage of the PEBB approach is the reduced cost of power electronic 5 P Embedded controller H P M U W N V M H U W Cell V N Cbus Cbus Figure 1.3: Topology of basic UPEC cell products, especially for the high volume products and those with low volume but high power level. Since all the converters in a large-scale power electronic system can be constructed based on one or several standard PEBBs, the development cycle of each converter will be significantly reduced. The costs and the time for developing the whole system will be driven down considerably. Other major benefits of the PEBB approach include increased redundancy, reliability, flexibility and easy maintenance. The UPEC cell that is proposed in this project is such a standard PEBB cell. It is a self-contained unit, consisting of a half bridge converter with IGBT switches and energy storage components such as inductors and capacitors. The basic topology of this cell is presented in Fig.1.3. It has six power terminals and one control bus. In different operation modes, these terminals are configured differently. 1.3 Parts of Mode of UPEC A combination of the basic topology of UPECs can be used to implement AC/DC, DC/AC, DC/AC, and AC/AC modes for single phase or three phases operation. Here, three operation configurations are introduced. 6 Figure 1.4: Topology of basic UPEC cell: AC/DC operation 1.3.1 AC/DC operation For the single phase AC/DC operation, W point is connected to H point, and V point is connected to M point, the topology for this connection is illustrated in Fig.1.4. For parallel inputs parallel outputs single phase configuration, each UPEC shares the single phase AC/DC operation’s connection, at the same time, all U, V, P and N points of each cell are connected separately. This configuration guarantees that each UPEC shares the same input and output busses, and thus processes a fraction of the total power. Serial inputs and parallel outputs of UPECs are employed to realize three phases operation, and P points and N points of each cell are connected separately. 1.3.2 DC/AC operation When the cell operates in DC/AC mode, V point is connected to M point, and U point is with V point as illustrated in Fig.1.5. The UPECs can implement parallel inputs parallel outputs operation, parallel inputs serial outputs operation and threephase operation[3]. 7 Figure 1.5: Topology of basic UPEC cell: DC/AC operation 1.3.3 DC/DC operation The DC/AC configuration can be easily converted to DC/DC operation by changing the control reference. The topology of DC/DC operation refers to Fig.1.5. As we know, a high switching frequency for a DC/DC converter can effectively reduce the passive components’ size and weight, which practically determine the power density of the converter. However, the high switching frequency operation of converters is prevented by the high switching loss in power devices and the high switching stress caused by circuit parasitics such as stray inductance. A soft switching configuration can be used to alleviate switching losses/stresses and increase the switching frequency of converter. Therefore, soft switching technique is employed for DC/DC operation of UPEC to increase the converter switching frequency and minimize the value of input inductance, thus increase packaging density of the cell. The topology of soft switching UPEC cell for DC/DC operation is displayed in Fig.1.6. 8 ✏ ✌ ✗ ✌ ✕✖ ✙✍✄ ☛✁ ☞✍✌ ☛ ✎ ✟ ✟✛✚ ✟✡✠ ✗ ✆ ✏✑✆ ☛✠ ✂✁ ✞ ✞ ✄ ✌ ☎✞ ✄✝✆ ☞ ✆ ✒✔✓ ✕ ✗ ✖ ✘ Figure 1.6: Topology of soft-switching UPEC cell: DC/DC operation 1.4 Scope of Thesis The main focus of this thesis is to look into design of UPEC cell for AC/DC operation. Since the idea of UPEC requires a basic cell topology for all operations, it is important that the design envelope for AC/DC operation is defined in terms of the cell parameters. Next, I need to identify the region of this parameters space which is common to other cell operation (DC/AC) to decide one basic cell. Subsequently, control strategies for AC/DC operation are designed. These methods of current control and their stability in terms of performance and implementation on digital signal processor are investigated. In the end, a UPEC cell designed for AC/DC operation is implemented in hardware, and experiments are carried out. A basic UPEC cell topology that can work in AC/DC while maintaining the constraints of DC/AC and DC/DC topology is verified. This thesis is organized as following: • Chapter 2, first I will look at a brief review on the work done for PEBB. The performance required for the AC/DC operation is then introduced. Single phase control methods and parallel control methods are reviewed. 9 • Chapter 3 introduces the basic UPEC’s operation for AC/DC mode. The parameter optimization of UPEC cell is conducted. Hardware and software implementation is illustrated. • Chapter 4 implements PI controllers for AC/DC operation, stability analysis is done for the controllers, and simulation results and experimental results are given. • Chapter 5 presents deadbeat controller for UPEC current control. The stability property, robust problems of parameter mismatch and using constant value of output voltage replacing the measured output voltage value are discussed. • Chapter 6 compares two current controllers. Democratic current sharing scheme is designed and simulated for two UPECs. • Chapter 7 gives conclusion and future work. 10 Chapter 2 Literature Review 2.1 The Investigation in the PEBB Programs PEBB are integrated subassemblies or modules that are capable of processing electric power [4]. It is the combination of common electrical, mechanical and thermal denominators, allowing the integration of all of these technologies. Depending on the instructions given to the controller, PEBB can function as, for instance, an inverter, a dc/dc converter, a rectifier or a motor controller. In the past several years, a lot of research has been done to develop PEBB [4], [5],[6],[7]. These approaches include hardware and software architecture, switching technique, packaging technique, and stability study for PEBB. 2.1.1 PEBB−A System Approach to Power Electronics Throughout the PEBB programs, many modern paradigms have been studies for adaptation to power electronics. They are open plug and play architecture, cellular design, hierarchical design[4],[8]. • Plug and Play Power The idea of an open plug and play architecture is to build power electronics 11 systems in much the same way as personal computers. Power modules would be plugged into their applications and operational settings made automatically. The application knows what is plugged into it, who made it, and how to operate with it. Each power module maintains its own safe operating limits. Realization of this vision will require a community to develop standard interfaces and protocols. • Cellular Design, PEBB Partitions Here we use a specific example to explain the concept of cellular design and PEBB partitions. An entire three-phase rectifier can be integrated into single clock or five-terminal PEBB, at power levels less than 100kW. At power levels greater than 100kW and less than 1MW, medium power range, the phase leg is the primary unit of integration-a three terminal PEBB. At much higher power range, the primary unit of integration is a switching cell or two-terminal PEBB. These primary blocks have electrical relationships, which transcend power ratings. Electrically, the bridge or five-terminal PEBB can be made of either three three-terminal PEBBs, or six two-terminal PEBBs. The three-terminal PEBBs can be made of two two-terminal PEBBs. These simple relations lead to a cellular description or organization of power electronics that applies equally to the bridge formed monolithically, or to the bridge built on three acres of land. The bridge, phase leg, and switching cell will be primary PEBBs and thus ”well posed” candidates for primary units of integration. Finally, these blocks would be snapped together to form equipment and systems. 12 • Hierarchical Design Integration and snapping elements together require intelligence and hierarchical control. Control partitions need to be defined to compliment the spatial partitions or blocks. Simply, it needs enough intelligence and control embedded into a switch cell or two-terminal PEBB to enable them to be snapped together to form higher order PEBBs. Starting with a switch cell, embedded intelligence is needed to allow two cells to be snapped together to form a voltage-source or current-source phase leg. A next layer of intelligence allows two voltage-source phase legs to form an H-ridge or three voltage-source phase legs to form a threephase bridge. Moreover, control architecture is temporal as well as spatial. The six main sections of power converter are the power switches, gate drive, power circuit or topology manager, application or load manager, system controller and filters. Each section operates predominately in a time as well as spatial domain. 2.1.2 Hierarchical Architecture of Plug and Play PEBB system Centralized digital controllers are commonly used in today’s power converter systems. However, the largest drawback of this kind of controller, the great number of point-to-point signal links that connect power stages and sensors on one side with the centralized controller on the other side, makes the modularization and standardization of power electronics system and subsystem very difficult [4]. For an effective design, a hardware-oriented design strategy is adopted. Additionally, the technology to be exploited should make itself affordable. Modularization of 13 the control structure and the building block meets these requirement. To design flexible, automatically configurable power electronic system control software, the control software will be functionally divided into hierarchical levels. By building modularized software objects within each level, standardizing interfaces between levels, the application software will be independent of the hardware specifications of power stage. As long as supporting the standardized interfaces between levels, products from different vendors can communicate and work with each other. Furthermore, if both sides of an interface support device self-identification and system resources assignment, the plug and play can be implemented at the interface. The control software can be divided into the following levels. • Application Manager (AM) Splitting the controller into power processing units and main controller, the main controller is defined as the application manager. It’s a high level controller, liberated from low level hardware oriented task, and is designed to provide system flexibility and re-configuration, which often performs high level control algorithm and supervisory task. By means of open, flexible and highbandwidth communication link the system will gain additional level of flexibility and adaptability. • Hardware Manage (HM) Within the integrated power module, the embedded control architecture together with gate drives, sensors and communication interface is defined as the hardware manager. The hardware manager handles all topology specific func- 14 tions, including the control of soft-switching circuity, and the general functions, such as PWM generation, signal sensing, A/D conversion and protection. • Communication Link The goal of communication protocol is to make the distributed controller system flexible, open , and modular. The more information communicated, the more flexibility this system achieves. Trade-off has to be established because of bandwidth limit of communication channel. Two types of information are communicated through network: real time data exchanged on switching cycle level, and initialization data exchanged during the system power up. For AM-HM levels, the control algorithm of a converter is specific. However, how to draw the software boundary between AM-HM levels accurately, for example, where a modulator should be implemented, has more than one solution. The boundary drawing can be arbitrary, which means functions implemented at each level and data transferred between hierarchies are well defined, no matter what kind of hardware is used at each level. A better solution allows boundaries to float somewhat between different systems and applications, so that higher system flexibility can be achieved. For example, if the HM has enough calculation capability, some calculation can be shifted to the HM level. Thus the workload of the AM can be reduced, while the HM can be more efficiently used. On the contrary, if the HM is as simple as a logical circuit of some data buffers and timers, the AM should take over the calculation work as much as possible. The data transferred through each interface will vary with the floating of software boundaries. If the boundary floating is achieved by software 15 instead of hardware, this method of interface definition will make the system structure more flexible and open without additional hardware requirement. 2.1.3 Dataflow Architecture for PEBB Traditional approach to embedded control software offers advantages of optimizing solutions for a particular application. Applications are common solutions that are tightly coupled to the hardware managed. However, significant effort is needed to adapt software from a previous system to the new system, and maintenance or modification of the majority of the code can be difficult and expensive. As software become more complex, managing the overall structure of the software − which is in mainprogram-and-subroutine style [5]. An alternative software architecture of dataf low is proposed. In the dataflow architecture, control applications are implemented as a set of execution processes. Dataflow processes communication by sending messages through one-way message queues called data ”flows” or channels. Dataflow is independent from each other, and only consumes data from some channels and produces results on other channels. These properties ensure minimal dependency and maximal flexibility between components. Fig.2.1 is an example of dataflow for an open loop control algorithm for a PEBB based 3-phase converter. The advantages of dataflow are listed below. • focus on constructing application from highly independent computational units that enables software reuse • enable a new approach to application reconfigurability 16 Figure 2.1: Dataflow graph of an open loop control algorithm for a PEBB based inverter • provide a natural mapping onto distributed software execution • foster the construction and population of a library of reusable components • provide ideal support for rapid application development 2.1.4 Switching Technique The parasitic inductance is mainly the stray inductance between the DC link and PEBB since the small internal PEBB parasitic inductance can be ignored. This parasitic inductance causes the high voltage or high current overshoot while the devices switch, which will damage the devices. It is difficult to make the parasitic inductance between the DC bus and PEBB (due to the physical distance) as small as possible. There are two ways to alleviate this problem: (1) slow down the current changing or force it to zero before switch turn on, (2) add a clamping capacitor to absorb the rapidly changing current of device and thereby reduce the rate of change of current in the parasitic inductance. To reduce hard switching voltage overshoot, a clamping capacitor is used. To reduce hard switching loss, a snubber directly in parallel with the device is sometimes used [9]. 17 Soft switching technique is employed to alleviate switching losses/stresses. So far, many soft switching topologies have been proposed. They can be classified into two basic categories: zero-voltage switching (ZVS) and zero-current switching (ZCS). ZVS reduces the switch turn-on loss by forcing the switch voltage to zero prior to its current flowing, while ZCS reduces the turn-off loss by forcing the switch current to zero to turn-off static value. PEBB soft switching is quite different from the conventional soft switching. Conventional soft switching technique always concerns the device itself, and only help to relieve the switching loss of the main devices. For PEBB, a soft switching technique is able to reduce the losses/stresses of the main devices. There are many soft switching topologies. Among them, the auxiliary resonant commutated pole (ARCP) converter [10] can achieve zero voltage for all main switches without significant modification to the hard-switching modulation scheme. The advantage of ARCP is that the auxiliary switches block only half the DC link voltage and are turned off under zero current conditions and therefore have a low power loss. The ARCP is one of the best ZVT topologies and a preferred soft switching technique for some specific applications. Zero-current transition techniques can significantly reduce turn-off loss and di/dt . The ZCT scheme in [11] eliminates the main switch turnoff loss. However it cannot help the switches reduce the diode reverse recovery and turn-on loss. Moreover, the auxiliary switch is turned off hard. To get rid of these problems, a newly proposed ZCT in [12] is very attractive for medium to high power application. This ZCT topology can not only eliminate the main switch turn-off loss but also reduce the turn-on loss and diode reverse recovery problem significantly. Besides, the auxiliary switches are all soft switched. 18 AC/DC AC/DC Line Input PFC Inverter HF AC bus Load Converter AC/DC Figure 2.2: AC distribution power system 2.1.5 Interactions and Stability PEBB approach is particularly suitable for the development of large scale power electronic system, such as DC, AC distributed power system and utility power conditioning system. In the distributed power system, interactions and instability problems may happen [13], [14], [15]. For example, for a PEBB-based AC distributed power system as shown in Fig.2.2, various loads are connected to the AC bus, even though the subsystems may be well designed for stand-alone operation, when these subsystems are integrated, the following issues still should be considered: • input filter subsystem interaction: the distributed filter can interact on the bus, and cause large signal ringing and transient on the bus • rectifier and inverter interaction: boost rectifier and inverter may be cascaded to form a two-converter subsystem with intermediate filter, low phase margin 19 Rout Vout IL Cout Lin Cout Cin Cbus Communication Bus Figure 2.3: Basic UPEC cell in the system can cause oscillations on the DC bus • bus impedance effect when the distance between the source and the load is long • ground-loop interaction for parallel modules • interaction between source and load for parallel modules because of source output impedance 2.2 Operation Principle and Control Methods Chapter 1 has introduced the concept of the universal power electronic cell (UPEC). The philosophy of UPEC is to design standard cells, which can implement any of converter operation modes such as AC/DC, AC/AC, DC/AC and DC/DC in single phase, paralleled phases and three phases. Here, basic operation modes of UPEC as a rectifier are analyzed. 2.2.1 The Basic UPEC Cell and AC/DC Operation A basic UPEC cell is shown in Fig.2.3. 20 Figure 2.4: operation modes of UPEC The cell operates in AC/DC mode. The operation modes of this half bridge circuit is illustrated in Fig.2.4. For Iin > 0, when switch 1 is on and switch 2 is off, the diode paralleled the switch 1 conducts current; when switch 1 is off and switch 2 is on, switch 2 conducts current. For Iin < 0, when switch 1 is on and switch 2 is off, switch 1 conducts current; when switch 1 is off and switch 2 is on, diode paralleled switch 2 conducts current. Whether the switches or the paralleled diodes conduct current depends on the polarity of the input current [16]. 21 v ref Voltage Controller iref Current Controller UPEC vo is Figure 2.5: Control diagram 2.2.2 PI control In this thesis close control loops are designed for UPECs. The objective of the current control loops is to regulate the input current at the reference value. The objective of the voltage loop is to maintain constant DC output voltage. The basic close loop control topology is illustrated in Fig.2.5. The current controller outlined for UPECs here are PI controller and deadbeat controller. PI controller has been widely used in all types of the feedback system, it’s simple and easy to implement, especially for the systems originally containing a single pole [17]. The PWM PI controller has the following advantages: 1) constant switching frequency; 2) good dynamic regulation; 3) low acoustic noise. A transfer function of PI controller can be indicated as G(s) = K τs + 1 τs (2.1) where K is the gain of PI controller, and τ is the integral time constant. Under close loop control, proportional constants and integral constants must be designed carefully, otherwise the system maybe become unstable. There are several ways to determine the integral gain and proportional gain of PI controller. In the conventional PI controller, these two parameters can be obtained from selecting a 22 desired damping ratio and settling time for a given settling band[18],[19]. In [20], the author employs the pole assignment technique to determine the gain of PI controller and the closed-loop dynamics is investigated by the root locus plots. The close loop control for UPEC AC/DC operation will be designed using PI controllers and analyze the digital PI controller at the continuous-time domain, thus consider effect of the hold and the delay time introduced by the ADC conversions and the Pulse Width Modulation (PWM) gain. Different from the methods stated above, the method of technical optimum was used to derive expressions for gains and time constants of PI current regulators[21]. At the same time, the effect of output voltage filter on the control system will be analyzed. 2.2.3 Deadbeat Control Deadbeat control method is a technique which predicts at the beginning of each modulation period for the evolution of the current error vector on the basis of the actual error and the load parameters. A steady state can be reached in n+1 samples, where n is the order of the controller, thus minimize the forecast error [22], [23], [24],[25]. Essentially, a deadbeat controller cancels all the poles of the system and replaces them with poles at the origin. Therefore, it should not be applied to systems with poles outside or in the vicinity of the united circle in the z plane. Thus, the deadbeat controller should be used only with stable plants or processes. The transfer function of a deadbeat controller is given by Gdb (s) = P0 + P1 z −1 + P2 z −2 + . . . + Pn z −n q0 + q1 z −1 + q2 z −2 + . . . + qn z−n (2.2) Typically, this technique relies on the model of the process, which also makes it 23 sensitive to the model uncertainties. In addition, dead-beat algorithms can be computationally intensive and thus require extensive processor resources. Nevertheless, deadbeat control offers a much faster dynamic response than conventional control and can be successfully applied to switching circuits. In this thesis, the concept proposed in [25] is employed to derive the deadbeat control law for UPEC cell current control. This technique has the advantage of being fairly simple to design and implement over a conventional control structure such as digital PI controller. The control method as well as the performance of UPEC and some performance constraint of DSP will be detailed in Chapter 5. 2.3 Democratic current sharing control scheme Paralleling power converters allow high current to be delivered to load without the need to employ the devices of high rating. Also, the parallel operation of converters increases system reliability, facilitating system maintenance, allowing for future expansion, and reducing system design cost. The main design issue in parallel converters is the control of sharing current in the parallelled converters. In democratic current control (also called central limited current control (CLC)), all converters are programmed to track the average converter output current, which is the total of output currents divided by the number of converters. Fig.2.6 illustrates the topology of this control. The controller needs to calculate the average current continuously, and each converter compares its output current with the average current, and then incorporates the error to the voltage control loop. An additional current controller is needed to realize it. The analysis of steady state current distribution error 24 G(s) K1 Gd1(s) P1(s) K2 Gd2(s) P2(s) Kn Q(s) W(s) Gdn(s) Pn(s) Figure 2.6: Block diagram of N parallel-connected converters under CLC scheme between nonidentical converter modules with the improvement of system reliability and efficiency by using CLC associated with a maximum current limit technique is presented in [26], [27]. Nonlinear phenomena of bifurcation under democratic control is discussed in [28]. The democratic current control is designed for two UPEC paralleling operation to increase the power capacity. I will simulate the paralleling operation in the later chapter. 25 Chapter 3 UPEC Cell and Parametric Selection In chapter 1, the concept of the universal power electronic cell (UPEC) was introduced. The philosophy of UPEC is to design standard cells, which can implement any of converter operation mode such as AC/DC, AC/AC, DC/AC and DC/DC in single phase, paralleled phases and three phases. Since UPEC is designed for different operation modes, the design values of passive elements of DC/AC operation may not be suitable for AC/DC operation. How much do the parameter values for an AC/DC application differ from the DC/AC and DC/DC converter? In this chapter, investigation is made for the variation of the performance of the AC/DC converter with respect to the values of its passive parameters, and optimal values of input inductor, input capacitor and output capacitors suitable for both AC/DC & DC/AC operation are calculated, also the hardware implementation using the chosen circuit parameters are stated. 3.1 Selection of Parameters The basic UPEC cell is displayed in Fig.3.1. 26 Rout Vout IL Cout Lin Cout Cin Cbus Communication Bus Figure 3.1: Basic UPEC cell 3.1.1 Output Capacitor Selection The cell is simulated under the following conditions. • Input AC voltage(peak value) : 230 Volts • Output DC voltage: 600 Volts • Output power: 600 Watt • AC frequency: 50 Hz • Switching frequency: 5 kHz-20 kHz In order to study the effect of input and output filter parameters on the respective performance criteria, a simulation of the UPEC with variation of parameters is carried out. The input capacitor value is varied as Cin = 0.001uF , 0.01uF , and 0.1uF , the input inductor value Lin ranges from 1mH to 7mH, and the output capacitors Cout is from 500uF to 2500uF . The relationship between input inductor, output capacitor and the input power factor is illustrated in Fig.3.2, Fig.3.3 and Fig.3.4. 27 1 PF 0.95 0.9 0.85 8000 6000 4000 Lin (uH) 2000 0 0 500 1000 1500 2000 2500 Cout (uF) Figure 3.2: Cout -Lin -PF relationship at Cin =0.001uF As the figures show, Fig.3.2 has the smoothest plot surface, with the increase of output capacitor’s value, power factor increase regularly, and Fig.3.4 has the roughest plot surface in the three figures, which means the change of the power factor is not regular. However, we still can see two trends in these figures. First, the power factor diminishes greatly with decrease in output capacitance especially below 1000uF . Second, the power factor increases gradually with the increasing input inductor. The input power factor does not alter much for large value of capacitors and inductors, but it really changes much when the value of output capacitors falls below 1000uF and the value of input inductor falls below 2000uH, and high value of input capacitor is not advisable at Cout < 1000uF . After analyzing these figures, it is not difficult to get the conclusion that output capacitors influence power factor mostly in these three parameters. Hence, for a UPEC, the output capacitor is the dominant factor that contributes to the input power factor. 28 1 PF 0.95 0.9 0.85 0.8 8000 6000 4000 Lin (uH) 2000 0 0 1000 2000 3000 Cout (uF) Figure 3.3: Cout -Lin -PF relationship at Cin =0.01uF 3.1.2 Input Inductor Selection Total Harmonic Distortion (THD) of input current is another main factor that is associated with power quality. In this section, the relationship between the input inductor, input capacitor and the THD is explored. Since power factor is lower when Cout is below 1000uF , I choose the values of the output capacitors Cout = 1000uF and 2000uF , and range the input capacitor from 0.01uF to 0.1uF , with the input inductor from 1mH to 7mH. The performances of the topology are indicated in Fig.3.5 and Fig.3.6. It can be seen from the figures that the plot surface of Fig.3.5 is rougher than that of Fig.3.5. The THD of input current changes regularly at larger value of output capacitors. When the input inductance falls below 1000uH, the value of output capacitors does not affect the THD much. Fig.3.7 gives the THD performance for Cin = 0.01uF . It illustrates the effect of the output capacitor on THD of input current. THD increases greatly with decrease in input inductance; and THD varies comparably little with increasing output capac- 29 1 PF 0.95 0.9 0.85 0.8 8000 6000 4000 Lin (uH) 2000 1500 0 500 2000 2500 1000 Cout (uF) Figure 3.4: Cout -Lin -PF relationship at Cin =0.1uF itance. Hence input inductor is the dominant factor that contributes to THD of input current. To get low output voltage ripple and high input power factor, and minimize the passive components’ size of UPEC cell at the same time, the following parameters for UPEC AC/DC operation has to be chosen: Lin ≥ 4.5mH, Cout ≥ 1000uF , and the performance of cell is not affected greatly without Cin . The design for DC/AC cell was carried out to satisfy the output voltage THD of less than 5% at 5 kHz switching frequency. The values of the capacitor and inductor obtained are Lout ≥ 6.74mH , Cout ≥ 3.76uF and Cdc > 600uF [3]. Here, Cout in DC/AC operation is the same capacitor with Cin in AC/DC operation, and Lout in DC/AC operation is the same inductor with Lin in AC/DC operation. If a higher value of inductor for the common design is chosen, it will not have any adverse effect on the THD performance of the AC/DC configuration. From former discussion, the smaller of Cin in AC/DC operation, the better of the cell performance, so Cin can be 30 0 0.5 Ithd 1 1.5 2 2.5 8000 0.1 6000 4000 Lin (uH) 0.05 2000 0 0 Cin (uF) Figure 3.5: Lin -Cin -T HD relationship at Cout =1000uF 0 Ithd 0.5 1 1.5 2 8000 6000 4000 Lin (uH) 2000 0 0 0.02 0.04 0.06 0.08 0.1 Cin(uF) Figure 3.6: Lin -Cin -T HD relationship at Cout =2000uF 31 0 Ithd 0.5 1 1.5 2 8000 6000 4000 2000 Lin (uH) 0 500 1000 1500 2000 2500 Cout (uF) Figure 3.7: Lin -Cout -T HD relationship omitted for AC/DC operation. This capacitor block will be added to standard cell if the cell works in DC/AC mode. Hence, the following parameter for UPEC AC/DC and DC/AC operation are adopted: • Input inductance of AC/DC mode (Output inductance Lout of DC/AC mode): Lin = 6.74mH • Input capacitance of AC/DC mode (Output capacitance Cout of DC/AC mode): Cin = 3.76uF • DC capacitor: Cdc = 600uF For AC/DC operation, the output capacitor, which is the DC capacitor in DC/AC mode, is much larger, thus capacitor block is added to standard cell when the cell operates in AC/DC mode. In the following part, I will discuss the circuit implementation. The control 32 method will be referred at the next chapter. 3.2 Circuit Implementation 3.2.1 Input Inductor Design The input inductor is constructed using product of EPCOS company (PM 114/93) which consists of the following components, and the inductor with the value of 6.7mH is assembled, the figure of the core is shown in Fig.3.8: • PM core type supplied in set, which is gapped with mounting dimensions 114 × 92 × 93mm3 • N27 for core material • Polyphenylene sulphide material for coil former The inductor is designed under the following conditions: • Peak winding current Imax 20A • Inductance L 6.7mH • Maximum operating flux density Bmax 500mT • Effective magnetic cross section Ae 17.20cm2 • Core window are WA 11.47cm2 • Winding fill factor Ku 0.7 • Frequency f 20 KHz 33 Figure 3.8: The topology of the inductor core 34 Determine air gap length lg = 2 µ0 LImax × 104 2 Bmax Ae = 7.8 × 10−3 (m) (3.1) Determine number of turns N = LImax × 104 Bmax Ae = 156(turns) (3.2) Evaluate wire size Aw ≤ Ku W A n ≤ 0.05146(cm2 ) (3.3) So AW G#11 (American Wire Gauge) for the diameter of the wire is chosen. Considering the dimensions of the inductor, it is not fixed on the PCB, and only the two connectors are soldered on the PCB. 3.2.2 Semiconductor Circuit AC power supply from KIKUSUI, PCR series, 1000L is employed to supply the rectifier. SEMICKRON SEMITOP2 IGBT Module SK20 GB123 is used. It integrates a half bridge with two IGBTs in the module. The maximum rating of the IGBT is Vces = 1200V , Ic = 23/15A, and a suitable heatsink is chosen. Rubycon Aluminium Electrolytic capacitors MXR Series − 105o C(P CBM ounting − Snap − In) 330uF/400V are used for capacitor blocks. 35 SEMIKRON Hybrid Dual IGBT Driver SKHI22 drives the IGBT Module, which gives two compensated signals to the upper and lower IGBTs, with +15V gate-emitter voltage for switch on, and -7V gate-emitter voltage for switch off. The hybrid driver comprises the short circuit protection and interlock time for two IGBTs in half bridge. Short circuit protection function is achieved by measuring the collector-emitter voltage, turn ”error” to ”low” with voltage smaller than 0.7V. The interlock time is set in order to prevent two switches from being in the on-state simultaneously. The locking time between the turn-on signal for one IGBT and the release the turn-off signal for the other is 3.25us, may be increased to 4.25us by applying a 15V supply voltage at Pin 9. High-speed dual optocoupler SFH6325 from Infineon technologies is chosen to couple signal to a electrically isolated drive circuit from the control circuit reference with respect to the control logic ground. CD4049 is employed to match the electrical level between DSP and IGBT driver. Isolated 3W DC-DC converter NDY0515 from C&D Technologies company is used to isolate digital ground from analog ground. The topology of the auxiliary drive circuit is plotted Fig.3.9. Technosoft TMS320F243 DSP Motion Starter Kit is employed to sense the stable variables, realizes the digital control methods, and produces IGBTs switching signals. The board is powered by 5V DC voltage, it has one event manager, which can start two timers, and give out total 8 PWM signals, and total 6 variables can be sensed by 6 ADC channels. Using DSP to realize control method offers many advantages over conventional analogue processing . 36 +5V +15V NDY0515 +5V +15V DSP +15V +15V CMP1 IGBT Driver SKHI22 CMP2 SFH6325 To IGBT CD4049 Figure 3.9: Auxiliary driving circuit topology • Stability - unaffected by temperature or ageing • Repeatability - not dependent on component tolerances • Power Consumption - generally lower, especially CMOS devices • Cost - lower system cost in many applications • Calibration - no calibration is required • Chip Count - can be reduced in many applications • Algorithms - many algorithms are difficult or impossible to implement in analogue technology 3.2.3 Sensor and scaling The input current is sensed by current transducer LA 25-NP, the input voltage and output capacitor voltages are sensed by voltage transducer LV 25-P, all from LEM company. The signals from sensors are first limited between -2.5V to +2.5V, and then these signals are sent to OP amplifier MC33174P, which reverses the polarity of 37 +15V +2.5V 5V Iin ADCIN RM -15V Figure 3.10: Current sensor and scaling topology the signals and gives 2.5V offset, therefore, the signals’ electrical level is from 0V to 5V. Fig.3.10 represents the hardware interface put in place to realize the described function. • 2.5V → 0V • 0V → 2.5V • −2.5V → 5V These signals are sensed by the on-chip A/D converters. The user software reads the digitized signals from the A/D converter result registers and saves them in temporary memory locations in a suitable fixed-point format. For a fixed-point DSP, these digitized signals are represented as numbers with finite word length, 10-word length for TMS320F243. The whole UPEC circuit schematics with PCB layout is shown in appendix A. The picture of the hardware is shown in Fig.3.11. 3.2.4 PCB consideration The parallelled capacitors block increases the value of output capacitance. Moreover, paralleling capacitors can be used for lowering the overall equivalent series re- 38 Figure 3.11: Hardware sistance (ESR) and equivalent series inductance (ESL) of output capacitors. This allows the resulting filter capacitor to source or sink high level of ripple current with much less internal heating. Here, the PCB board layout has a direct effect upon how much ”sharing” occurs in the current and heating of the paralleled capacitors. The physical characteristics of the PCB layout between the other components in the loop and each capacitor must be as identical as possible. If the layout is not identical, the capacitor with the lower series trace impedance will see higher peak currents and become hotter (i2 R). To promote the sharing, there should be a layout symmetry to both leads of the paralleled capacitors. The area between the IGBTs and capacitors should be as small as possible to reduce the impedance of the circuit loop. A low impedance circuit reduces the sensitivity to dVDS dt at turn off of the switches. The circuit loop to be reduced includes the two half-bridge IGBTs, and is illustrated in Fig.3.12. 39 inductive loop to be reduced Figure 3.12: Inductive loop to be reduced Another problem concerned with when I designed this PCB is EMI problem. The very short rise and fall times of voltages and currents in power electronic converters lead to a significant level of energy in emissions. Moreover, the increasing di/dt values produced by the new generation of switching devices increase these voltage spikes, this becomes the main source of conducted and radiated noise emission. Except for the aforementioned problems, the following conditions should be considered when designing the PCB: • use of double sided PCB where each high current path is immediately above its returns path on the other side of the board • making all of the high current traces as short, direct, and thick as possible • choose components specified with a low internal inductance • the inductor, output capacitors, and output diode should be put close to each 40 other to reduce the EMI radiated by the power traces due to the high switching currents through them • place large areas of ground plane on both sides of the PCB and around these high current traces, the ground planes act as electro-radiated EMI and dissipate them within eddy currents created by the RF energy • place the power components so that during each of the two states the current loop is conducting in the same direction, this prevents magnetic field reversal caused by the races between the two half-cycles and reduces radiated EMI • capacitive coupling of the AC node voltages into their nearby ground planes • use parallel grounding scheme for sensitive analog circuitry and use series grounding scheme for less sensitive analog circuitry • run the gate signals in parallel to the corresponding source of IGBTs • isolate analog from digital grounds 3.2.5 Hardware Controller Implementation The DSP architecture to implement the controller is shown in Fig.3.13. The clock module provides the time base for the DSP operation. There are two clock domain in clock module, one is the CPU clock domain consisted of the clock for most of the CPU logic, and the other is the system clock domain consisted of the peripheral clock and the clock for the interrupt logic in the CPU. Event Manager (EV2), analog and digital converter (ADC), Internal and External Interrupt Modules of DSP are employed to 41 realize the digital control to UPEC single phase. General Purpose (GP) Timer1 is configured for continuous up-counting mode or continuous up/down-counting mode, and used to provide the time base for PWM generation, ADC sampling, interrupt service routine (ISR), current and voltage control loops. Interrupt mask registers IMR, EVIMRA are configured to allow Timer1 to generate an interrupt on period match. Once the DSP core receives the INT2 Timer1 interrupt, it takes a finite amount of time for interrupt source identification and context saving. Following that, T1 timer matches ISR, ADC conversion starts and the results are saved. The input voltage, input current, and two output capacitor-voltages are sampled by ADC channels, and the signals are then fed back to the DSP core, and stored in the most significant 10-bit of ADC data register 1 and 2, respectively, which are two-level FIFO. Since total two ADC channels can be configured in ADC Control Register 1 every time, four state variables need two cycles of configuration of ADC Control Register 1. After ADC finishes conversion, the sampled data are loaded to system-interface module, and then passed onto the data bus. The program controller sends the order to CPU, CPU loads sampled data from the data bus according to the order, and begins calculation. In CPU, accumulator and product register (PREG) are both 32-bit, and can be employed for addition, subtraction and multiplication directly. For the division operation, additional programm is needed. During the arithmetic calculations, CPU keeps contact with the data bus, and downloads the variables from the data memory or store the updated values to the data memory. After finishing calculation, CPU transfers the results to the full compare registers. During the interrupt service routine, GP timer1 keeps counting, and when the counting number matches the value of the 42 DARAM B0 DARAM Data Bus EEPROM Program Bus Memory Control Program Controller Interrupts Initialization Event Manager General Purpose Time CPU Full compare units Clock Module System-Interface Modue PWM1 . . . PWM6 Interrupts Reset Peripheral Bus 10-bit ADC 10-bit ADC 10-bit ADC 10-bit ADC Iin Us Vcap1 Vcap2 Watchdog Timer Figure 3.13: DSP architecture compare register, PWM waveform takes action to change their polarity from 0 volt or 5 volts or vice versa. There are total three full compare registers in the Event Manager module, and each compare register can give out two complementary PWM waveform. For controlling UPEC single phase operation, only one compare register is used. Programmable precise dead times are provided between this pair of complementary PWM signals. This dead time is defined by the dead-time control register DBTCON. DSP architecture for processing sample data and implement the control method is displayed in Fig.3.13. 43 3.2.6 Problem of Output Voltage Ripple According to [29], the output voltage ripple can be expressed as δV0 (t) = − P0 sin 2ωt ωCV0 (3.4) From the equation 3.4, we can see that when output power, and output voltage and line frequency is constant, the output voltage ripples are inversely proportional to the value of the output capacitor. Hence, one method to reduce the output voltage ripple is to employ very large output capacitors. However, large capacitor means large dimension, which will affect the integration of UPECs. Another choice is to tune a digital controller of voltage feedback loop to have a sluggish response, on the other hand, for higher performance, a notch filter can be used. In this thesis, a notch filter is used to filter out the line frequency harmonics. The topology of the notch filter is illustrated in Fig.3.14, the three capacitors must have identical value, and the fixed resistor must be six times the adjustable resistor [30]. This filter has a gently sloping attenuation away from the notch and infinite attenuation (assuming perfect matching of component values) at the notch frequency. The notch frequency is given by fnotch = 1 2πC 3R1 R2 (3.5) In this design, the voltage across each capacitor is sensed, hence two notch filters for sensing each capacitor voltage with the notch frequency of 50Hz is required. The following parameters values are employed: R1 = 56KΩ, R2 = 6KΩ, C = 0.1uF for the filters. 44 6(R1+R2) in out C C C R1 R2 Figure 3.14: Notch filter 3.2.7 Problem of Inrush Current Inrush current is another problem which has to be faced. When switching power supplies are first turned on, they present high initial currents as a result of high dV dt to the filter capacitor impedance. These large filter capacitors act like a short circuit, producing an immediate inrush surge current with a fast rise time. The peak inrush current can be several orders of magnitude greater than the circuit’s steady state current, and lasts for less than 1/2 a normal 50 Hz cycle. Without protection, the only limits on the amount of inrush current drawn is the line impedance, and capacitor equivalent series resistance. If the inrush current is not limited, it may burn out fuses, damage connector pins, cause glitches in the input voltage, and generate high di/dt and dv/dt. Therefore, the peak current and current ramp must be controlled. Here, several methods are given to achieve inrush current control: • Inrush current control by a resistor A series input resistor shunted by a triode AC switch (Triac) or silicon controlled 45 rectifier (SCR) is an efficient approach. However, a control circuit is necessary. This method can function on a cycle by cycle basis for protection after a dropout. • Using negative temperature coefficient (NTC) thermistor NTC thermistors are thermally sensitive semiconductor resistors which exhibit a decrease in resistance as absolute temperature increases. NTC thermistor may be put in series with the switching converter to limit the inrush current. At turn on, the thermistor presents a high resistance to inrush current. As it self-heat, the resistance begins to drop causing a negligible voltage drop in the circuit. However, because NTC thermistor heat after they suppress inrush currents, these devices require a cool-down time after power is removed. This cool-down or ”recovery” time allows the resistance of the NTC thermistor to increase sufficiently to provide the required inrush current suppression the next time it is needed. If the circuit has to be switched at a frequency that does not allow NTC thermistor to cool down completely, its inrush current limiting ability is impaired. • Start-up bypass rectifier This is implemented by adding an additional rectifier bypassing the boost inductor. The bypass rectifier will divert the startup inrush current away from the boost inductor 46 Chapter 4 Closed loop control of UPEC using PI Controllers 4.1 Single Phase Close Loop Operation Using PI controllers The main tasks of control loops are to regulate the output voltage and the input current. The input current dynamics is faster than the output voltage dynamics, hence a cascaded control is used. For the voltage loop, a digital PI controller is employed to maintain the output voltage at the reference value. It calculates the voltage error between the voltage references and the sampled output voltages. The output of the PI control gives the peak value of the reference current, hence the phase of the voltage, sinωt is multiplied to this value to obtain the reference for the input current. The current reference is compared with the sampled current, the error is controlled by the inner current regulator, here, a PI regulator is used for current control. The output of the current controller compares with a triangle waveform of desired switching frequency, which produces the switching signals for two IGBTs. The topology of the control loop is displayed in Fig.4.1. 47 Cout iL Vout Lin Cout Cin Comparator G ( Z )i i ref sinwt V out V ref iL G ( Z )V Figure 4.1: Cascaded closed loop control 4.1.1 Input current controller For the input current loop, the plant is an equivalent continuous-time model taking into account the effect of the hold and the delay time introduced by the ADC conversions. The plant, approximated by a first-order element, with a time constant equal to one half of the sampling period Ts and a gain of KP W M . To further simplify the control block in Fig.4.2, the two blocks with the smallest time constants (sample and hold, and PWM ) are grouped together to form a single block with gain KP W M and equivalent time constant of Teqi , the equivalent time constant is determined as following: (Ts s + 1)(0.5Ts s + 1) = 0.5Ts s2 + (Ts + TP W M )s + 1 (4.1) 48 Figure 4.2: Block diagram of the current control loop Figure 4.3: Block diagram of the simplified current control loop Since 0.5Ts s2 is very small, hence, it can be omitted. We defines Teqi ≈ Ts + TP W M = 1.5Ts (4.2) Here, TP W M is the time constant of the PWM [21]. The resultant system is given in Fig.4.3, the dominant pole in the load can be canceled by setting the integral time constant of the PI regulator equal to that of the load, so τi = L/R (4.3) The resulting open loop transfer function is Wop (s) = Kpi KP W M Rτi s(1.5Ts + 1) (4.4) Therefore, the closed-loop transfer function becomes Wci (s) = 1 1+ Rτi s Ki KP W M + 1.5Ts Rτi 2 s Ki KP W M (4.5) 49 Choosing the damping factor ε = 0.707, then the proportional gain Kip and integration gain Kii as Kip = Ki = Kii = = Rτi 3Ts KP W M (4.6) Kip τi R 3Ts KP W M (4.7) for the given system we get Kip = 0.074 , and Kii = 1.11. The bode plot of the closed loop for current control is depicted in Fig.4.4. The regulator has a bandwidth of 600Hz for −3dB attenuation, which ensures its stable operation. 4.1.2 Output Voltage Controller without Notch Filter Since the term of 1.5Ts Rτi Ki KP W M is very small, the s2 term can be neglected. Hence the closed transfer function can be simplified as Eq.4.8 Ws = 1 1 + 3Ts s (4.8) The DC voltage control loop can be modeled with the block diagram of Fig.4.5. The current loop is approximated by the first order function Eq.4.8. As in current control loop, Teqv can be obtained by combining the sample and hold time constant and current loop time constant, as in Eq.4.16 (Tv s + 1)(1 + 3Ts s) = 3Ts Tv s2 + (Tv + 3Ts )s + 1 (4.9) 50 Figure 4.4: Bode plot of the current closed loop Figure 4.5: Block diagram of the voltage control loop without notch filter 51 Since the term of 3Ts Tv is very small, the s2 term can be omitted. We define Teqv = Tu + 3Ts (4.10) The open loop transfer function is wcv = Kvp (Tv s + 1) CTv s2 (Teqv s + 1) (4.11) The following parameters can be obtained [21] Kvp hv + 1 = 2 Teqv C 2Teqv (4.12) and h= Tv Teqv (4.13) thus Kv = (h + 1) 2Teqv Tv (4.14) From the above equation, we can get Kv = 4.67. 4.1.3 Closed loop simulation results Simulation is performed to test the closed loop system. The reference of the output voltage is chosen to be 600 volts. The steady state performance of the system is shown in Fig.4.6 and Fig.4.7. The dynamics of the system is also explored. Firstly, the load is changed from 600 Watt to 1200 Watt at 0.35 second from the beginning of the simulation. The simulation results are shown in Fig.4.8. Secondly, the reference voltage is changed from 52 Figure 4.6: Input current and voltage 610 output voltage/V 605 600 595 590 585 580 0.25 0.3 0.35 0.4 time/sec 0.45 Figure 4.7: Output voltage 0.5 53 610 output voltage/V 605 Tf 600 595 590 585 580 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.6 0.65 0.7 time/sec Figure 4.8: Output voltage under the load changing from 600W to 1200W 15 Input current (A) 10 5 0 −5 −10 Tf −15 0.3 0.32 0.34 0.36 0.38 Time (sec) 0.4 0.42 Figure 4.9: Input current under the load changing from 600W to 1200W 54 670 Output Voltage (V) 660 650 640 630 620 610 600 590 0.3 Tf 0.4 0.5 Time (sec) 0.6 0.7 Figure 4.10: Output voltage under the reference voltage changing from 600V to 650V 600V to 650V at the 0.35sec from the beginning of the simulation. The performance of the output voltage is illustrated in Fig.4.10. Fig.4.9 and Fig.4.10 indicate that the input current responds faster than the output voltage, this is because the dynamics of input current loop is faster than the dynamics of output current loop. From the simulation results, the task of the control system is achieved, the output voltage is maintained at the reference value, and the input current tracks the input reference current. 4.2 Output Voltage Controller with Notch Filter The output voltage has a ripple of twice the line frequency. This ripple can not be easily controlled and is present due to the nature of rectification. Hence, a notch filter is used to filter out this constant frequency disturbance. As with the voltage loop without notch filter, Teqv can be obtained by combining the sample and hold time constant and current loop time constant, as in Eq.4.16, and 55 Figure 4.11: Block diagram of the voltage control loop Figure 4.12: Block diagram of the simplified voltage control loop the equivalent control loop is displayed in Fig.4.12 (Tv s + 1)(1 + 3Ts s) = 3Ts Tv s2 + (Tv + 3Ts )s + 1 (4.15) Since the term of 3Ts Tv is very small, the s2 term can be omitted. Thus, Teqv = Tv + 3Ts (4.16) The notch filter has the transfer function in Eq.4.17 Hnotch = K(s2 + ω02 ) s2 + s wQ0 + ω02 (4.17) The open loop transfer function is wcv = Kv (Tv s + 1) K(s2 + ω02 ) × CTv s2 (Teqv s + 1) s2 + s wQ0 + ω02 (4.18) Symmetrical optimum method in [31],[32] is used to synthesize the control system. 56 The following parameters can be gotten h= Tv Teqv (4.19) C hTeqv K (4.20) The gain at the crossover frequency is Kv = √ h = 5.76 will result in a damping factor D = 0.707 for the closed loop function [31],[32]. From the above equation, we can get Kv = 2.08. 4.3 Analysis of the Power Factor According to [29], the output voltage can be expressed as the summation of a DC voltage and a voltage ripple v0 = V0 + ∆v0 (t) (4.21) The closed loop is set up, PI controller is employed to control the output voltage loop. The difference of the output voltage and the reference voltage is sent to the controller. Subsequently we can get the output of the PI controller as [33]: ipi = Ipi + ∆ipi (t) (4.22) Ipi = Kv (Vo − Vo,ref ) (4.23) and 57 ∆ipi (t) = Kv ∆v0 (t) (4.24) Kv is the gain of the controller Then ipi (t) multiplies the phase of the input voltage, we can get the input current reference iref = ipi × sin ωt = (Ipi + Kv ∆v0 (t)) × sin ωt = Ipi sin ωt + Kv P0 sin 2ωt sin ωt ωCV0 1 sin 2ωt sin ωt = [cos ωt − cos 3ωt] 2 (4.25) (4.26) The input current reference is expressed as iref = Iref sin(ωt + θ) − Kv P 0 cos 3ωt 2ωCV0 (4.27) in which Iref = 2 Ipi +( θ = tan−1 Kv P 0 2 ) 2ωCV0 (4.28) Kv P 0 2ωCV0 Ipi (4.29) The power factor can be obtained using the power balance principle as PF = = IL1,rms cos θ IL,rms Iref Kv P0 2 (Iref )2 + ( 2ωCV ) 0 cos θ (4.30) 58 1 y−PF 0.95 0.9 0.85 500 1000 1500 x−Cout(uF) 2000 2500 Figure 4.13: PF according to Formula which is plotted in Fig.4.13. The plotted curve almost coincides with the curve in Fig.3.3, so the conclusion in the third section, the output capacitor is the dominant factor among the passive parameters that contribute to the input power factor, is proved. 4.4 Controller Implementation The internal structure of the DSP for the PI realization is displayed in Fig.4.14. The sampled two output capacitor voltages from ADC channel 2 and 3 are compared with an internal voltage reference, and then two errors are added together as Verr , Verr is sent to the CPU, and there PI voltage controller is implemented. The results of the PI voltage control multiply the sampled Vs from ADC channel 4, this product acts as the current reference for the inner current loop. The sampled current of ADC channel 5 is subtracted from the reference current, the resulting current is fed to the PI current controller. The output of this current regulator is a command voltage, and is used to 59 Figure 4.14: DSP internal structure and sensing Interface Block Diagram for PI controllers determine the duty cycle of the PWM gating signals. This current regulator output is passed to the PWM module through the full compare register CMPR3. When the PWM module compares this value with a triangle waveform generated internally by Timer1. The result of the comparison is the required PWM signals PWM5 and PWM6. The main programming flow chart for PI control is illustrated in Fig.4.15, and the interrupt program flow chart is illustrated in Fig.4.16. 4.4.1 Pulse-Width-Modulation The energy that power supply delivers to load through a switching power converter is controlled by PWM signal, which is applied to the gates of the IGBTs. PWM signals are pulse trains with fixed frequency and magnitude, and variable pulse width. There is one pulse of fixed magnitude in every PWM period. However, the width of the pulses changes from pulse to pulse according to a modulating signal. When a PWM signal is applied to the gate of a power transistor, it causes the turn on and turn off intervals of the transistor to change from one PWM period to another PWM period. 60 start initialize _stop variable load and initialize timer1 registers: - load _timer_period variable and store it to T1PER register - reset timer counter register (T1CNT) - set timer cofiguration register (T1CON) - configure timer 1 in continuous-up-down mode, DSP internal clock, prescaler X1 - disable timer 1 feature to automatically start ADC conversion (in GPTCON) program ADC module: - set ADC configuration register (ADCCTRL2) - configure the ADC control & status register (ADCCTRL1) - clear ADC stacks (ADCFIFO1 and ADCFIFO2) program PWM module: - set PWM deadbeat parameters (DBTCON) - define active state of the 2 PWM outputs (ACTR) - load initial varaible and store it to CMPR1 register - set Compare Units control register (COMCON) load the address of timer 1 interrupt service routine into the corresponding interrupt vector and store it to tpint1vec vector initilize the variables Kp and Ki for current and voltage PI regulator calculation umask INT2 and T1PINT to enable timer 1 period interrupts generation (IMR, IMRA and IFRA) start PWM generation: - enable compare operation in Compare Units (in COMCON register) - enable output pins of Comapre Units (in COMCON register) - start timer 1 (in T1CON register) loop: call monitor NO stop ? YES end Figure 4.15: Main programming flow chart 61 _t1per_ISR: Timer 1 Interrupt Serivce sampling feedback current and voltages : - start ADC conversion immediately (ADCCTRL1 register) for V_cap1 and V_cap2 - keep checking ADCEOC bit to wait for the end of conversion (ADCCTRL1 register ) - save ADC results - configure ADCCTRL1 for V_s and I_s - keep checking ADCEOC bit to wait for the end of conversion (ADCCTRL1 register ) - save ADC results execute the voltage control algorithms to generate the current commands for the current control loop execute the current control algorithms to generate the modulation signal if V_ref = max_Vref_trgt, Vref = V_ref - calculate the PWM duty cycles and save the values in the specified full compare shadow registers (CMPR3) - the compare registers are updated after the period match return from ISR Figure 4.16: Interrupt program flow chart 62 asymmetric PWM PWM period PWM period PWM period PWM period symmetric PWM Figure 4.17: Asymmetric and symmetric PWM signals Fig.4.17 illustrates two types of PWM signals, asymmetric and symmetric. The pulses of an asymmetric PWM signal always have the same side aligned with beginning or end of each PWM period. While for symmetric PWM signal, the pulses are always symmetric with respect to the center of each PWM period. It is found that symmetric PWM signals generate less harmonics in the output voltages and currents [34]. In rectifier circuit, we would like the input current of the rectifier to be sinusoidal with magnitude and frequency controllable, therefore SPWM technique is employed. To get a sinusoidal input current at a desired frequency, sinusoidal control signal (the modulating wave) at the desired frequency is compared with a triangular waveform (the carrier waveform) displayed in Fig.4.18. The frequency of the triangular waveform determines the rectifier switching frequency. 63 Figure 4.18: Symmetric PWM scheme 64 (Vin ) h Vd 2 1.2 1.0 0.8 m a = 0 . 8 , m f = 15 0.6 0.4 0.2 0.0 1 mf mf +2 2m f 2mf +1 3mf 3mf + 2 Figure 4.19: Harmonics spectrum The amplitude modulation ratio ma is expressed as ma = Vˆmod Vˆcar (4.31) where Vˆmod is the peak amplitude of the modulating signal, and amplitude of carrier waveform Vˆcar keeps constant. The frequency modulation ratio mf is defined as mf = fs f1 (4.32) fs is the frequency of the carrier waveform, and f1 is the modulating frequency. It eliminates all harmonics less than or equal to 2K − 1 where ”K” is the number of pulses per half cycle of the sine wave. Moreover, the harmonics are pushed to the range around the carrier frequency and its multiples. The harmonics spectrum is plotted in Fig.4.19. 4.4.2 Natural and Regular Sampling The SPWM method outlined uses a sine reference waveform in comparison with a triangular carrier waveform to determine the switch transition points. This method is called ’natural sampling’ technique. It is simple to understand and even simple to 65 Figure 4.20: Uniform sampling topology implement with analog circuitry. However, digital implementation is rather difficult. The main difficulty is in determining the intersection points between the triangular wave and the sine wave, this requires solving a transcendental equation in real time. To overcome this problem, a simple implementation method called regularsampling is adopted in digital control to determine the switching instants. Here, the magnitude of the modulating signal vmod is sampled and held constant by a zero-order-hold over a switching period. Thus, the reference wave vmod is modified to the sample and hold version b. It is the signal b that is compared with the carrier waveform and used to determine the pulse widths. Thus the widths of the pulses are proportional to the modulating reference waveform at uniformly spaced sampling times. This is why this method is know as regularsampling. Fig.4.20 illustrates the topology of regular sampling theory. The modulating signal can be expressed as 66 vmod = ma sin(ωmod t) (4.33) where, ma is modulation ratio, and 0 ≤ ma < 1, then from the Fig.4.20, the following formula can be obtained 1 + ma sin(ωmod tD ) 2 = δ/2 Tc /2 (4.34) Tc (1 + ma sin(ωmod tD )) 2 (4.35) then δ= and δ 4.5 1 (Tc − δ) 2 Tc = (1 − ma sin(ωmod tD )) 4 = (4.36) Experimental Results for PI control Hardware results were got under the following conditions • Input voltage (peak value): 80V • Output voltage: 320V • Frequency: 50Hz The experimental results for the rectification operation without control are shown in Fig.4.21 and Fig.4.22, the simple rectifier based AC/DC converter produces poor 67 Figure 4.21: Experimental results of input voltage and input current when no switches action Figure 4.22: Experimental results of output voltage when no switches action power factor and line current distortion. Input current for starting up is displayed in Fig.4.23, in this case the input voltage was gradually increased using a programmable AC source. Fig.4.24 illustrates the voltage across IGBT change at turn off under 4.3A current, and the overshoot voltage is about 20 volts. This demonstrates the low leakage inductance design of the power circuit. 68 Figure 4.23: Experimental results of input current at startup Figure 4.24: Voltage across IGBT when turn off 69 Figure 4.25: Experimental results of input voltage and input current with notch filter at 5kHz switching frequency Figure 4.26: Experimental results of input current without notch filter at 5kHz switching frequency The input current performance with notch filter and without notch filter for 5kHz illustrated in Fig.4.25, and Fig.4.26, respectively. The ripple in the output voltage will be transmitted to the current loop when the bandwidth of the voltage loop is high. Since we cannot reduce the bandwidth of the voltage loop, this problem is solved by using the notch filter to filter out the output voltage ripple. Input current performance with and without notch filter at 10kHz are displayed in Fig.4.27 and Fig.4.28 respectively, the harmonics of the current is reduced compared with the operation at 5kHz. 70 Figure 4.27: Experimental result of input current with notch filter at 10kHz switching frequency Figure 4.28: Experimental result of input current without notch filter at 10kHz switching frequency Table 4.1: Control performance comparison for PI controller 0 T HDi (%) PF Output voltage ripple(V) ∆V × 100% V0 with filter 5kHz 10 0.97 2.6 (V0 = 320V ) 10kHz 5.1 0.98 2.6 (V0 = 320V ) without filter 5kHz 35 0.89 2.7 (V0 = 320V ) 10kHz 20 0.93 2.7 (V0 = 320V ) rectifier operation 94 0.72 7.6 (V0 = 150V ) 71 Figure 4.29: Experimental result of output voltage Table 4.1 shows that THD is lowered by increasing the switching frequency, thus, the power factor is increased. The circuit performs much better with notch filter than without notch filter. The output voltage is shown in Fig.4.29. 72 Chapter 5 Closed Loop Control of UPEC using Deadbeat and Hysteresis Controllers 5.1 Single Phase Close Loop Operation Using deadbeat current controller In Chapter 2, the basic deadbeat control law has been reviewed. In this chapter, I will derive the deadbeat control law for UPEC, and look into the implementation of the deadbeat control law, the performance of UPEC as well as some performance constraints of DSP. Let us consider the UPEC cell, and assume for simplification that the output filter capacitors are large enough to consider the output voltage constant. The switching frequency will be made high enough so that the assumption of constant output voltage holds true even with the line related frequency ripple of the output voltage. For dead-beat controller, the UPEC has two states of operation according to the actions of two switches, as shown in Fig.5.1. Since the switching frequency is generally much higher than the input voltage frequency, Vs can be assumed constant over one switching period. The inductor current over one switching cycle can be expressed by 73 Figure 5.1: Operation states of UPEC the following equations [25],[35],[36],[37],[38]: When switch S2 is on iL (t) = iL (tn ) + 1 L (vs + vc− )dt tn ≤ t ≤ tn + D(n)T s iL (t) = iD(n)Ts + 1 L (vs − vc+ )dt t(n) + D(n)Ts ≤ t ≤ t(n + 1) (5.1) (5.2) (5.3) (5.4) So i(n + 1) = i(n) + Vs Ts V0 D(n)Ts Vc+ Ts + − L L L (5.5) 74 iref (n+1) 1 2L V0 (n) * TS K PWM 2 VS D (n) 1/ R 1+ ( L / R)s is (n) Delay Unite Vo Figure 5.2: Deadbeat current control diagram where V0 (n) = Vc+ (n) + Vc− (n) (5.6) then, the duty ratio of the switching cycle nth can be expressed as D(n + 1) = 2Vs − 2Vc+ (n) 2L(iref (n + 1) − iL (n)) − D(n) − V0 (n) × Ts V0 (n) (5.7) and 0 ≤ D(n + 1) < 1 (5.8) The above equation can be simplified by Eq.5.9, considering the two capacitor voltages are almost equal, the current control loop diagram is illustrated in Fig.5.2 D(n + 1) = 2L(iref (n + 1) − iL (n)) 2Vs − D(n) − +1 V0 (n) × Ts V0 (n) (5.9) The trailing-edge pulse-width modulation method illustrated in Fig.5.3 is used to determine the switch actions in deadbeat current controller. The switch control signal g(t) is produced by comparing the control variable vc (t) with a trailing edge saw-tooth signal νsaw (t). Under this modulation, the lower switch is turned on at the beginning of each switching cycle, and turned off after time DTs , where D is the switch duty ratio. The lower switch then stays off for the remainder of the switching cycle. The upper switch acts complementary with lower switch in every cycle. 75 Figure 5.3: Trailing edge modulation In DSP, trailing-edge pulse width modulation is realized by configuring the GP timer as continuous Up-Counting mode. After getting the duty ratio, this value is sent to full compare shadowed register, and the compared register is uploaded after the period match. PWM waveform changes its electrical level after one timer clock cycle of the match between the compare register and the timer counter. For trailing-edge pulse width modulation, compare match happens only once every interrupt routine, while in SPWM modulation, it happens twice every interrupt routine. 5.1.1 Design Constraints for Deadbeat Control • Stability property of the trailing edge modulation Stability properties of the deadbeat control under trailing edge modulation can be shown with the reference to the waveforms of Fig.5.4[25]. The solid line shows the input current waveform in steady state, while the dashed line shows the input current with a perturbation ∆i at the beginning of the switching 76 Figure 5.4: Deadbeat control under trailing edge modulation period n. The effects of the predicted duty cycle D[n + 1] can not be observed until the next switching period. Thus the perturbation ∆i exists. With the next duty ratio D[n + 1], the deadbeat current reaches the reference iin by the end of the (n+1)th switching period. The initially assumed perturbation disappears. Hence, there is one sample time delay in the correction of the error. • Effect of using constant output voltage value in current loop Though deadbeat current control requires a sampled value of output voltage, it is possible to simplify the current control loop by using a constant value of output voltage. The effect of this assumption on the control of current is studied. From the control law in Eq.5.7, we can see that the deadbeat control depends on the assumptions that the inductance, switching period and output voltage are known. DSP’s system clock is used to determine the switching period, and usually the variation of switching period is relatively insignificant. Using a 77 constant value of sampled output voltage instead of the sampled instantaneous value, we neglect the influence of the output voltage ripple, which will avoid the division and reduce the calculating time, see Eq.5.9. Assume that ∆v, the error between the measured output voltage and the assumed constant voltage value, appears in the control system, it results in errors in the input current and duty cycle ∆i and ∆D, respectively. The duty cycle calculated using the constant value is D (n + 1) = 2Vs 2L(iref,n+1 − (iL,n + ∆i)) +1 − Dn − (V0 + ∆v) × Ts V0 + ∆v (5.10) and D(n + 1) is calculated using the measured voltage, hence ∆D(n + 1) = D (n + 1) − D(n + 1) 2L(iL,n + ∆i) 2iL,n L 2Vs,n 2Vs + − + (V0 + ∆v) × Ts V0 Ts V0 + ∆v V0 2Vs,n ∆v 2L∆v∆i − = − V0 (V0 + ∆v)Ts V0 (V0 + ∆v) = − (5.11) because ∆v is very small respect to V0 , we get ∆D(n + 1) = − 2L∆v∆i 2Vs,n ∆v − V02 Ts V02 (5.12) The perturbed current caused by the ∆D(n + 1) can be expressed as ∆i(n + 1) = 2∆v∆i 2Vs,n ∆vTs + V0 V0 (5.13) setting ∆i(n + 1) = ∆i then, we can get ∆i = 2∆v 2Vs,n Ts × V0 − 2∆v L (5.14) 78 0.7 Error Current (A) 0.6 0.5 0.4 0.3 0.2 0.1 0 0 20 40 60 Error Voltage (V) 80 Figure 5.5: relationship between ∆i and ∆v Eq.5.14 is plotted in Fig.5.5. It can be seen that 2∆v V0 −2∆v is very small, which will result in small value of ∆i, and can be neglected for most of cases, for example, the error of 20V can only results in no more than 0.1A error in the input current. Therefore, using the constant value in the current control loop to replace the sampled output voltage is reasonable. 5.1.2 Simulation Results Deadbeat current controller is employed for the simulations, and PI controller is designed for the voltage loop, the diagram of the output voltage control loop is shown in Fig.5.6. The UPEC is simulated for the close loop operation. Fig.5.7 illustrates input current response under the input current reference from 5.21A to 10.42A at the 0.35 second. Fig.5.8 illustrates output voltage response under the output voltage reference changed from 600V to 650V. The simulation results shows that fast dynamic current loop response is achieved, and the output voltage is regulated at the reference value. 79 Figure 5.6: Output voltage control loop 15 Current (A) 10 5 0 −5 −10 Tf −15 0.32 0.33 0.34 0.35 0.36 0.37 0.38 0.39 0.4 Time (sec) Figure 5.7: Input current response under the input current reference from 5.21A to 10.42A for deadbeat current controller 670 Output Voltage (V) 660 650 640 630 620 610 600 590 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.6 0.65 0.7 Time (sec) Figure 5.8: Output voltage response under the output voltage reference changed from 600V to 650V 80 Figure 5.9: Input voltage and input current at switching frequency 20kHz Table 5.1: Control performance comparison for deadbeat controller 0 × 100% T HDi (%) PF Output voltage ripple(V) ∆V V0 10kHz 201 0.49 2.8 (V0 = 200V ) 20kHz 106 0.68 2.8 (V0 = 200V ) 5.2 Experimental results The experiment results at the following condition is shown in Fig.5.10, and Fig.5.11: – Input voltage (peak value): 50V – Output voltage: 200V – Line frequency: 50Hz We can see that THD is very high in the deadbeat control, this is caused by large distortion appearing in the waveform, and high THD results in very low power factor. Increasing the switching frequency can reduce the THD, and improve power factor. The reason why the distortion appears will be discussed in the next section. The performance comparison is illustrated in Table 5.1. 81 Figure 5.10: Input current at switching frequency 10kHz Figure 5.11: Output voltage 2 Duty Cycle 1 0 −1 −2 0.2 0.25 Time(s) Figure 5.12: Duty cycle 0.3 82 5.2.1 The Performance of Deadbeat Control under Constraints In the experimental results in Fig.5.10, it is clear that there is distortion in the current waveform especially at the peak of the negative half cycle. This problem is produced by the saturation in the duty cycle. The duty cycle for this control should range from 0 to 1. However at low switching frequency, the approximation of Eq.5.7 leads to large error, and produces a lot of noise in the duty cycle as displayed in the Fig.5.12. This problem is not seen in simulation as the simulation uses a large resolution for duty ratio. On the other hand, the DSP uses only 16 bit fixed point representation. When implementing the control method using a DSP, a sampled value is stored in the compare register. This value may be larger than the value of period register, and cause the saturation of the duty cycle waveform. This will cause the switch that is on to remain on, and distort the input current. When the saturation happens in the upper cycle of duty cycle, the distortion appears in the negative cycle of the input current, and when the saturation happens in the lower cycle of duty cycle, the distortion appears in the positive cycle of the input current. This problem can be overcome by increasing the switching frequency and sampling frequency. The maximum PWM frequency that the DSP TMS320F243 can generate is 40kHz, this frequency is only suitable for very short programme. For the programme length in our case, the needed calculation time is long, so the DSP cannot finish all computations in the sampling period for 40kHz. On the other hand, if the control update is slower than the PWM frequency, the system become unstable. The maximum sampling frequency with deadbeat control that gives stable operation is about 20kHz. 83 The saturation of the duty cycle in DSP results in another problem. When the input voltage is increased, the saturation in the duty cycle will produce larger distortion in the current. When this larger distortion is fed back to the DSP, more saturation is produced, and then the distortion worsens, even causes the stability problem in the control system. This prevents the increase in the input supply voltage in the experiment. Hence, the operating input voltage for deadbeat control is kept at 50V. 5.3 Hysteresis Current Controllers In fixed band hysteresis current control, the hysteresis band i varies sinusoidally over a fundamental period, the input current is controlled within this band about the reference current by proper switch operations, as shown in Fig.5.13 [39]. In Fig.5.13, when the current increases, and reaches the band of iref + i/2, the lower switch is turned off, and the upper switch is turned on; when the current goes down and hits the band of iref − i/2, the lower switch is on, and the upper switch is off. Whether the switches or its paralleled diodes conduct current is determined by the polarity of iL . For hysteresis control, we can get the expression of the each switching cycle as L Vout ∆iL = − Vs sin ωt Ts 2 (5.15) hence, the required sampling period can be gotten as Ts = L∆iL V0 /2 − Vs sin ωt in our simulation, the smallest sampling period happens at sinωt = −1 Ts = L∆iL V0 /2 − Vs sin ωt (5.16) 84 Figure 5.13: Hysteresis current control scheme 15 Current (A) 10 5 0 −5 −10 Tf −15 0.32 0.33 0.34 0.35 0.36 0.37 0.38 0.39 Time (sec) 0.4 Figure 5.14: Input current response with hysteresis current control scheme 85 670 Output Voltage (V) 660 650 640 630 620 610 600 590 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.6 0.65 0.7 Time (sec) Figure 5.15: Output voltage response with hysteresis current control scheme = 6.7 × 10−3 × 2.5 300 + 230 = 3.184 × 10−5 (5.17) thus, the resulting maximum sampling frequency is fs = 1 Ts = 31.4kHz (5.18) With the long programme length, this sampling frequency cannot be achieved in DSP TMS320F243. 86 Chapter 6 Comparison of Controllers Performance 6.1 Comparison of Controllers Performance In the former chapters, PI controllers and deadbeat controller are implemented for the hardware using DSP. Hysteresis control can be implemented by analog controller, however, this control results in high sampling frequency of 31.4kHz for the design. With the long programme, the DSP can not respond for this high frequency. Hence, hysteresis current control is not implemented using a DSP. Moreover, uniform hardware is needed, so no additional hardware can be added to the UPEC cell, hence, hysteresis control is not implemented for hardware. Table 6.1: Control performance comparison for PI controller deadbeat controller at different operation voltage PI Deadbeat Input voltage(V) 80 50 Output voltage(V) 320 200 Maximum switching frequency(Hz) 10k 20k THD(%) 8.8 106 PF 0.98 0.68 Output voltage ripple (V) 8.6 5.5 Variables to be sensed 4 4 Programme length(lines) 431 368 Switching technique SPWM Trailing edge modulation 87 SPWM technique is employed for PI control and the trailing edge modulation technique is used for deadbeat control, Using SPWM technique, PI can achieve 10kHz switching frequency in DSP TMS320F243, and using trailing edge modulation technique, deadbeat can get 20kHz switching frequency. As the saturation problem occurs in the deadbeat control, it keeps the maximum operation voltage of 50V for deadbeat control, while PI control can achieve higher input operation voltage. The saturation problem also causes the large current distortion in deadbeat control, which results in large THD in current compared with PI control. At the same time, large THD reduces the power factor. Due to the higher output voltage, the output voltage ripple of PI control is larger than that of deadbeat control, but the ∆V0 V0 is smaller. Both these control method need to sense four state variables, input current, input voltage, and two capacitor voltages. Voltage ripple causes bad performance in the PI controller, distorting the input current, reducing the power factor. However, voltage ripple does not affect the deadbeat control much as the voltage ripple is neglected in the current loop calculation. When using the constant value to replace the measured voltage in the current loop, the error of 20V can only cause 0.122A current error in the current, and the error of 6V causes 0.003A current error. Hence the deadbeat control has a better stability than PI control. The total programme length for PI controllers is longer than for deadbeat controller. The comparison table for PI current controller and deadbeat current controller operating at the same input voltage level is also listed. Considering all of the items in Table 6.1, PI control gives superior performance. The advantage of the deadbeat controller is compromised by the saturation in DSP 88 Table 6.2: Control performance comparison for PI controller deadbeat controller at the same operation voltage PI Deadbeat Input voltage(V) 50 50 Output voltage(V) 200 200 Maximum switching frequency(Hz) 10k 20k THD(%) 6.5 106 PF 0.98 0.68 Output voltage ripple (V) 5.6 5.5 realization. It seems that increasing the switching frequency can improve the deadbeat controller performance, however, the maximum switching frequency can be implemented in DSP TMS320F243 is about 20kHz. The performance of the two controllers is shown in Table 6.2, the switching frequency of deadbeat control has to be kept higher to achieve a smaller current ripple. The other method to compensate the saturation will be studied in the future. 6.2 Parallel operation of two UPECs Parallel operation of UPECs is introduced to increase output power capacity. Democratic current-sharing scheme is employed to force the current in each UPEC tracking the average current, which is the total load currents of two UPECs divided by the number of paralleled module [26]. Fig.6.1 is the topology of democratic currentsharing scheme. The controller needs to calculate the average current continuously, and each converter compares its output current with the average current, and then incorporates the error to the voltage control loop. An additional current controller is needed to realize it. In this design, the error between the load current and average current is passed through P (z)i (i=1,2), and then added into the output voltage 89 Vref Vout Vref 1 iref 1 G ( Z )V UPEC iout 1 Z Vout i L1 Sin w t Vref G(Z )i P(z)1 U1 P(z)2 U2 Sin w t Vref 2 G ( Z )V Vout iref 2 G ( Z )i UPEC iL 2 iout 2 Z V out Figure 6.1: Topology of control method control loop. The load is changed from 1000watt to 1600watt, the dynamic performance of the input currents is illustrated in Fig.6.3. At the same time, the circuit of two nonidentical UPECs is simulated, which is explored in Fig.6.4. The dynamic performance of the input currents is explored in Fig.6.5. A conclusion from the simulation results can be achieved that the load current is shared averagely by two UPEC even when two UPEC cell has different parameters. 90 10 Current/A 5 0 −5 −10 0.4 0.42 0.44 0.46 Time/sec 0.48 0.5 0.42 0.44 0.46 Time/sec 0.48 0.5 10 Current/A 5 0 −5 −10 0.4 Current/A Figure 6.2: Input currents of two identical UPECs 20 0 0.4 0.44 0.48 0.4 0.44 0.48 0.44 0.48 Current/A (UPEC1) −20 0.36 10 0 Current/A (UPEC2) −10 0.36 10 0 −10 0.36 0.4 Time/sec Figure 6.3: Input currents of power supply and two identical UPECs under load change from 1000 watt to 1600 watt 20 0 −20 0.52 10 Current/A (UPEC1) Current/A 91 0.6 0.64 0.56 0.6 0.64 0.6 0.64 0 −10 0.52 10 Current/A (UPEC2) 0.56 0 −10 0.52 0.56 Time/sec Figure 6.4: Input currents of power supply and two nonidentical UPECs Figure 6.5: Input currents of power supply and two nonidentical UPECs under load change from 1000 watt to 1600 watt 92 Chapter 7 Conclusion and Future Work 7.1 Conclusion PEBBs have many advantages as elements in power electronics systems. Based on the PEBB concept, large-scale power electronics systems are much easier to implement. The PEBB approach not only reduces cost, but also leads to high redundancy, high reliability, high flexibility and easy maintenance. In this thesis, the concept of UPEC is developed. A combination of the basic topology of UPECs is able to implement different modes converter operations. I focus on AC/DC single phase operation in this thesis. Several fundamental research issues have been identified and the respective general contributions are summarized as follows: • Prototype hardware implementation Since UPEC is a universal cell which can implement AC/DC, DC/AC and DC/DC operation modes, I need to find out the optimal circuit parameters for these operation modes. In this thesis, not only optimal parameters for AC/DC operation are gotten, but also compatible parameters with other oper- 93 ation modes are achieved. The estabilishment of prototype circuit provides the chances to test the control methods designed for UPEC. • PI closed loop control method PI controller with and without notch filter have been developed for AC/DC operation of UPEC. Theoretical and simulation results shows that PI controller with notch filter and higher swiching frequency presents superior performance, which embodies at lower input current THD, higher PF and lower output voltage ripples. It appears that the notch filter attenuates the output voltage ripple’s impact on the voltage control loop. The operation at lower switching frequency generates higher harmonic error amplitudes in current, and the distortion may deteriorate the dynamics of the linear current control loop. Experimental results prove the concept of the proposed technique. • Deadbeat closed loop control method Another control method, deadbeat technique, is also designed and implemented for UPEC. The simulation and experimental results prove that this control give fast dynamic response. The reason for its fast response is that there is only one sample time delay in the correction of the error between predicted current and the current in the steady state. Calculation reveals that perturbed current caused by parameter’s mismatch is very small, and can be omitted at some extent. The experimental results of deadbeat control is compromised by the DSP switching frequency saturation. This is one topic that we need to study 94 Figure 7.1: AC/DC/AC operation topology deeper in the future. 7.2 Future Work In the future work, we will use UPECs to implement some power electronic converters which attract great interest of power electronic industry. The topics for future work includes: • Design the AC/DC/AC operation using two UPECs, the topology is illustrated in Fig.7.1 AC/DC/AC can serve as the main power stage of an uninterruptible power supple (UPS), AC cycloconverter, AC line conditioner. The demand for AC/DC/AC converters with input power factor correction is growing rapidly. Two UPEC cells will be employed to implement it. And circulation current existing in the parallel converters should be considered. • Implement parallel input parallel output UPECs for AC/DC operation Parallel redundant operation of UPEC cells allows high current to be delivered to load without need to employ devices of high VA rating. We will apply the designed current sharing scheme in Chapter 6 to the hardware. 95 • Design control method for three-phase operation by UPECs Three-phase rectifiers are very popular in power industry. Three-phase rectifier can be realized by employing three UPEC cells in the form of series input and parallel output. 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Niu Pengying; Ashwin M Khambadkone; Ramesh Oruganti; the Fifth IEEE International Conference on Power Electronics and Drive Systems . PEDS 2003, 17-20 Nov 2003, , pp. 904-909. 103 Appendix A Circuit and Layout Scheme 104 AC V2 R3 24K -HT +HT L 6.7mH +15V LEM LV 25-P in -15V out LEM LA 25-NP Rm3 +15V -15V Control part DSP TMS320F243 .. .. Rm4 9 8 +5V CMP1 CMP2 SW S1 11 S2 14 U8 C+ 2000uF C2000uF NDY0515 SK20GB123 6 C9 100uF R4x 100 Load . 8 7 6 5 +15V C7 100uF SFH6325 1 2 3 4 U7 C5 15p R1 24K 1KVA R2 24K R2x 4.1K C6 15p +HT -HT -HT +HT R1xx 4.1K LEM LV 25-P 8 R3xx 10K -15V +15V +15V 2 4 -15V CD4049 LEM LV 25-P 1 3 5 U6 Rm1 Rm2 R6 10K . . p14 13 12 11 10 9 8 7 U5 SKHI 22 GND Vs Vin1 Rtd1 /Error Rtd2 Vin2 GND Vce1 S20 Cce1 15 Gon1 14 Goff1 13 12 9 E2 E1 Goff2 8 7 Gon2 6 Cce2 Vce2 1 R10x 1K R11 1K R13 10 R15 10 R14 10 R16 10 +5V R20 56K +5V R33 56K R9 56K 12 5 6 13 R36 56K R22 56K R29 56K +5V R25 56K +5V R40 56K C3 330pF R12 24K C4 330pF R17 24K + R10 18.6K U4A X1 MC33174-C - R21 56K R30 18.6K + U4B 14 7 +15V 1 U4D U4C X3 MC33174-A R23 18.6K R32 56K X2 MC33174-D + - 3 2 - R28 56K R37 18.6K X4 MC33174-B + R39 56K 9 8 +5V +5V R19 10 D1 1N4148 D2 1N4148 R31 10 D5 1N4148 Vin Iin V+ V- D8 1N4148 D7 1N4148 D4 1N4148 D3 1N4148 R38 10 D6 1N4148 +5V +5V 14 11 X4x SKM150GB063D 6 105 106 [...]... differently 1.3 Parts of Mode of UPEC A combination of the basic topology of UPECs can be used to implement AC/ DC, DC /AC, DC /AC, and AC/ AC modes for single phase or three phases operation Here, three operation configurations are introduced 6 Figure 1.4: Topology of basic UPEC cell: AC/ DC operation 1.3.1 AC/ DC operation For the single phase AC/ DC operation, W point is connected to H point, and V point is... of DC /AC operation may not be suitable for AC/ DC operation How much do the parameter values for an AC/ DC application differ from the DC /AC and DC/ DC converter? In this chapter, investigation is made for the variation of the performance of the AC/ DC converter with respect to the values of its passive parameters, and optimal values of input inductor, input capacitor and output capacitors suitable for. .. Cell and Parametric Selection In chapter 1, the concept of the universal power electronic cell (UPEC) was introduced The philosophy of UPEC is to design standard cells, which can implement any of converter operation mode such as AC/ DC, AC/ AC, DC /AC and DC/ DC in single phase, paralleled phases and three phases Since UPEC is designed for different operation modes, the design values of passive elements of. .. ground-loop interaction for parallel modules • interaction between source and load for parallel modules because of source output impedance 2.2 Operation Principle and Control Methods Chapter 1 has introduced the concept of the universal power electronic cell (UPEC) The philosophy of UPEC is to design standard cells, which can implement any of converter operation modes such as AC/ DC, AC/ AC, DC /AC and DC/ DC in... operation 1.4 Scope of Thesis The main focus of this thesis is to look into design of UPEC cell for AC/ DC operation Since the idea of UPEC requires a basic cell topology for all operations, it is important that the design envelope for AC/ DC operation is defined in terms of the cell parameters Next, I need to identify the region of this parameters space which is common to other cell operation (DC /AC) to decide... switches are all soft switched 18 AC/ DC AC/ DC Line Input PFC Inverter HF AC bus Load Converter AC/ DC Figure 2.2: AC distribution power system 2.1.5 Interactions and Stability PEBB approach is particularly suitable for the development of large scale power electronic system, such as DC, AC distributed power system and utility power conditioning system In the distributed power system, interactions and instability... employed for DC/ DC operation of UPEC to increase the converter switching frequency and minimize the value of input inductance, thus increase packaging density of the cell The topology of soft switching UPEC cell for DC/ DC operation is displayed in Fig.1.6 8 ✏ ✌ ✗ ✌ ✕✖ ✙✍✄ ☛✁ ☞✍✌ ☛ ✎ ✟ ✟✛✚ ✟✡✠ ✗ ✆ ✏✑✆ ☛✠ ✂✁ ✞ ✞ ✄ ✌ ☎✞ ✄✝✆ ☞ ✆ ✒✔✓ ✕ ✗ ✖ ✘ Figure 1.6: Topology of soft-switching UPEC cell: DC/ DC operation. .. threephase operation[ 3] 7 Figure 1.5: Topology of basic UPEC cell: DC /AC operation 1.3.3 DC/ DC operation The DC /AC configuration can be easily converted to DC/ DC operation by changing the control reference The topology of DC/ DC operation refers to Fig.1.5 As we know, a high switching frequency for a DC/ DC converter can effectively reduce the passive components’ size and weight, which practically determine... decide one basic cell Subsequently, control strategies for AC/ DC operation are designed These methods of current control and their stability in terms of performance and implementation on digital signal processor are investigated In the end, a UPEC cell designed for AC/ DC operation is implemented in hardware, and experiments are carried out A basic UPEC cell topology that can work in AC/ DC while maintaining... phase, paralleled phases and three phases Here, basic operation modes of UPEC as a rectifier are analyzed 2.2.1 The Basic UPEC Cell and AC/ DC Operation A basic UPEC cell is shown in Fig.2.3 20 Figure 2.4: operation modes of UPEC The cell operates in AC/ DC mode The operation modes of this half bridge circuit is illustrated in Fig.2.4 For Iin > 0, when switch 1 is on and switch 2 is off, the diode paralleled