ADVA CED MATERIALS A D OVEL DEVICES FOR CMOS APPLICATIO S WA G HUIQI, GRACE A THESIS SUBMITTED FOR THE DEGREE OF Ph.D (E GI EERI G) GRADUATE SCHOOL FOR I TEGRATIVE SCIE CES A D E GI EERI G ATIO AL U IVERSITY OF SI GAPORE 2009 ABSTRACT Conventional transistor scaling becomes increasingly challenging beyond the 90nm technology node New approaches for the improvement of integrated circuit performance are needed This thesis documents novel ways to introduce strain in transistor channel New device structure and new materials are needed to boost carrier mobility and enhance drive current Chapter of this thesis documents techniques of forming high germanium (Ge) content substrates using Ge condensation technique Substrates with high Ge concentration could be employed in stress inducing structures or for high mobility channel transistors Chapter focuses on strained Si n-FET where tensile strain in the channel is induced by lattice mismatched Si or Si:C S/D stressors and high stress tensile nitride liner The Si:C S/D may be potentially adopted in future technology nodes Chapter documents another new approach of having a strain transfer structure beneath the channel to couple high stress from the S/D to the channel After the carrier mobility has been improved significantly, series resistance may become a performance limiter In Chapter 5, we thus explore in situ doped Si0.979C0.021 S/D stressor that mitigates the need for ion implantation, and enables higher activated dopant concentration A higher substitutional carbon concentration in Si:C was also used to increase the channel strain Chapter and report the formation of SiGeSn and GeSn formed by Sn implantation and anneal The compressive strain in the channel induced by the SiGeSn S/D increases the effective mobility of holes, and boost p-FET performance i In summary, novel devices employing novel strain engineering techniques were studied They show promising potential for augmenting the performance of conventional CMOS transistors ii ACK OW LEDGEME TS I would like to express my sincere gratitude to God and my religion for his guidance, love and compassion showered to me, throughout my years of studies and life and for showing me the direction in times of helplessness This thesis is dedicated to God God facilitated in the completion of this thesis and provided significant guidance to my life I owe more than words can describe to God My steadfast belief in the existence of God leads me towards the correct track in all times I see my God as a boundless salvific nature and who is present to liberate me from ignorance and suffering I would like to express my sincere gratitude to my advisor, A/Prof Yeo Yee-Chia for his generous help throughout my study at National University of Singapore (NUS) Prof Yeo is an admirable academic professional He taught me not only his precious knowledge, but also his exceptional professionalism and dedication to research He impressed me very much by his spirit, responsibility, passion and attitude in training students His drive is truly admirable I remember he once told me “Your passion in research should escalate with age” This truly reminded me I should not give up, and should persevere no matter how much failure or uncertainties I encounter in future He always provided timely support in difficult times, and gave me opportunities to present my work at important conferences Despite the hectic research life, he gave me time to appreciate life outside research I learnt many important aspects of life from him, and learnt to work as a team Throughout my life I will benefit from the experience and knowledge I gained working with Prof Yeo iii I am also grateful to my thesis advisors, A/Prof Zhu Chun Xiang from the National University of Singapore and Dr Subramanian Balakumar who had been very supportive of my work I thank them for serving on my thesis committee Special thanks to Dr Patrick Lo for facilitating my fabrication work at the Institute of Microelectronics (IME) I also thank the research staffs and engineer assistants at IME for their support I thank the staff for always giving me priority when using their equipments, and appreciate it when they stay back just to help me complete my processes I am also indebted to Dr Foo Yong Lim, Dr Debbie Seng, Dr Sudhinranjan Tripathy, Mr Lim Poh Chong, Ms Vivian Lin Kaixin from Institute of Materials Research and Engineering (IMRE) for their valuable guidance and insightful suggestions which are indispensable for my research work All of them are well known scientists and are always there to share their experience in materials analysis for my devices’ use I thank them for allowing me to use their X-Ray Diffraction (XRD) tool, Raman tool, TOFSIM tool and Hall measurement tool I also thank them for their patience in teaching me and enjoy their friendly discussions I would like to thank Dr Tripathy for proof-reading my thesis, with his invaluable suggestions, I incorporated them in this thesis and learnt from him in the process I would also like to thank Dr Wang Xincai from Singapore Institute of Manufacturing Technology (SIMTECH) On many occasions, he had sacrificed his personal time to provide timely support and guidance and to ensure timely deliveries of my work I sincerely appreciate his help and support rendered all these years whenever I need to use his laser equipment iv I would also like to take this opportunity to express my heartmost gratitude to Mr Chan Taw Kuei, and Prof Osipowicz from Physics Department (NUS) for giving me unlimited access to their Rutherford Backscattering tool I thank Taw Kuei for providing me with the data analysis and for always giving me priorities in completing the samples’ analysis I would also like to take this opportunity to thank my working partner, Dr Toh Eng Huat who introduced me to simulations, process developments and shared his expertise in simulations He impressed me by his enthusiasm towards research, and his intelligence, wit and ambition to accomplish them Special thanks goes to Dr Tan Kian Ming for his encouragements and for livening the tense research atmosphere and I benefited immensely from the discussions we had; my colleagues at the Silicon Nano Device Laboratory (SNDL), for providing a wonderful research atmosphere to work in It is my pleasure to acknowledge and thank my final year project colleagues, Grace Thng Shiwei, Charanya Kailash, Mabel Soe Wah Wah I appreciate their help in fabricating, measuring and deriving the characterization plots for my transistors as part of their final year projects I enjoyed the discussions with them and it was wonderful sharing my experiences and knowledge with them I learnt a lot from them, and gained immensely from their creative perspectives and ideas I derived enthusiasm and their burning passion for research from them I hope they, too, had a great time working with me v I would like to show my appreciation to the Agency of Science Technology and Research for financially supporting my course of my studies in NUS since my undergraduate days I would also like to show my appreciation to Agency of Science Technology and Research for providing me with overseas conference presentation opportunities and they had even given me a chance to present at the A*Star’s first inaugural graduate student conference I thank Prof Barry Halliwell, Prof Justine Burley for showering me with care and concern throughout my years of studies I would also like to thank Prof Miranda Yap and Dr Chirsitna Chai for their concern Last but not least, I would also like to thank my friends from NGS, Siew Lay, Winston, Swee Jin, Jacelyn Finally, I owe more than words can describe to my daddy, my mummy and my lovely brother, Henry I thank them for their care and love in my entire life, and thank daddy and mummy for the sacrifices they have made and support throughout my education They have been very supportive of me in all situations and under all circumstances,though they are often not recognized but are undoubtedly essential for my endeavours I thank Henry for his concern for me, and calling me every now and there on skype despite his hectic studies at Cornell University, New York Though he is physically distant from me, I appreciate and feel that he is always by my side, supporting and encouraging me even when things are not in my favor I owe more than words can describe to my family, and friends, Joan, Kaifen, Hanni, Cuilin, Fangying and Peichin vi TABLE OF CO TE TS ABSTRACT i ACK OW LEDGEME TS iii TABLE OF CO TE TS vii LISTS OF FIGURES xi LISTS OF SYMBOLS A D ABBREVIATIO S xxv CHAPTER Literature Review 1.1 Motivation 1.2 Background 1.3 Strain engineering for mobility enhancement 1.4 Electron transport in Strained Si n-FETs 1.5 Global and Local Strain Effects 1.6 Objectives of the research 13 1.7 Outline of the thesis 14 CHAPTER Ge condensation to form SGOI substrates 2.1 Introduction 17 2.2 Experimental Procedure 19 2.3 Materials and Strain State Analysis 24 2.4 Summary 25 CHAPTER Fabrication and Characterization of Strained SiGe n-FETs with Si or SiC S/D Stressors 3.1 Introduction 26 3.2 Strained SiGe n-FETs with Si Source Drain Stressors 26 vii 3.2.1 Background 26 3.2.3 Stress Simulation of strained Si MOSFET devices 29 3.2.4 Electrical Characterization of strained Si MOSFET devices 30 3.3 Strained n-FETs with Source/Drain Stressor and Tensile Liner 35 3.3.2 Device Fabrication 35 3.3.3 Stress Simulation of Strained n-FET with SiC S/D 36 3.3.4 Electrical Characterization of Strained n-FET 37 3.4 Summary 40 CHAPTER Strained Channel MOSFETs featuring Stress Transfer Layer and Source/Drain Stressors for Enhanced Performance 4.1 Introduction 41 4.2 Strained n-FETs featuring Stress Transfer Layer 42 4.2.1 Background 42 4.2.2 Strained MOSFET Structure Fabrication 43 4.2.3 Stress Simulation 46 4.2.4 Device Characterization and Analysis 48 4.3 Strain-Transfer Layer for Increased Strain Effects in p-FETs 51 4.3.1 Background 51 4.3.2 Concept of Strain Transfer in p-FET 51 4.3.3 Stress Simulation of p-FETs featuring SOI STL 53 4.3.4 Device Fabrication 54 4.3.5 Electrical Results and Discussion 56 4.4 Summary 59 CHAPTER In-situ doped SiC:P Source/Drain stressors for n-FETs 5.1 Introduction 60 5.2 Device Fabrication 61 5.3 Materials Characterization of SiC:P film 64 5.4 Stress Simulation of SiC S/D n-FETs 67 5.5 Device Characterization and Analysis 67 viii 5.6 Conclusion 70 CHAPTER Strained SiGeSn and GeSn formed by Sn implant 6.1 Introduction 71 6.2 SiGeSn formation by ion implantation and laser anneal 72 6.2.1 Background 72 6.2.2 Fabrication of SiGeSn Film 73 6.2.3 Materials Characterization and Analysis 74 6.3 GeSn Film Formation by Ion Implantation and Anneal 78 6.3.1 Background 78 6.3.2 GeSn Film Fabrication 78 6.3.3 Material Characterization and Analysis of GeSn film 80 6.4 Summary 89 CHAPTER Strained p-FETs with Sn Implanted S/D Regions 7.1 Introduction 90 7.2 Optimization of process conditions for Increased Strain Effects 91 7.3 Strained SiGe channel p-FETs with SiGeSn S/D 93 7.3.1 Fabrication of SiGe channel p-FETs with SiGeSn S/D 93 7.3.2 Materials Characterization of SiGeSn and Analysis 96 7.3.3 Electrical Characterizations and Performance Evaluation 98 7.4 Strained SOI channel p-FETs with SiGeSn S/D 100 7.4.1 Background 100 7.4.2 Fabrication of Strained SOI p-FETs with SiGeSn S/D 100 7.4.3 Electrical Characterizations and analysis 102 7.5 Summary 105 CHAPTER Conclusion 8.1 Summary 106 8.2 Ge condensation to form SGOI substrates 106 8.3 Strained n-FETs with Si or Si:C S/D Regions 107 ix [81] S Takagi, T Irisawa, T Tezuka, T Numata, S Nakaharai, N Hirashita, Y Moriyama, K Usuda, E Toyoda, S Dissanayake, M Shichijo, R Nakane, S Sugahara, M Takenaka, N Sugiyama, “Carrier-Transport-Enhanced Channel CMOS for Improved Power Consumption and Performance,” IEEE Trans Electron Devices, v 55, no 1, pp 21-39, 2008 [82] G H Wang, E.-H Toh, A Du, G.-Q Lo, G Samudra, and Y.-C Yeo, "Strained silicongermanium-on-insulator N-MOSFET with embedded silicon source and drain stressors," IEEE Electron Device Letters, v 29, no 1, pp 77-79, 2008 [83] G H Wang, E.-H Toh, Y.-L Foo, S Tripathy, S.Balakumar, G.-Q Lo, G S Samudra, and Y.-C Yeo, "Uniaxial Strained Silicon n-FETs on Silicon-Germaniumon-Insulator Substrates with an e-Si0.7Ge0.3 Stress Transfer Layer and Source/Drain Stressors for performance enhancement," 37th European Solid-State Device Research Conference (ESSDERC), Munich, Germany, pp 311-314, 2007 [84] R A Donaton, D Chidambarrao, J Johnson, P Chang, Y Liu, W K Henson, J Holt, X Li, J Li, A Domenicucci, A Madan, K Rim, C Wann., “Design and Fabrication of MOSFETs with a Reverse Embedded SiGe (Rev e-SiGe) Structure,” IEEE International Electron Device Meeting Technical Digest, pp.439, 2006 [85] Y.-C Yeo, “Enhancing CMOS transistor performance using lattice-mismatched materials in source/drain regions,” Semiconductor Science and Technology, no 22, pp S177-S182, 2007 [86] K.-W Ang, K.-J Chui, H.-C Chin, Y.-L Foo, A Du, W Deng, M.-F Li, G Samudra, N Balasubramanian, and Y.-C Yeo, “50 nm silicon-on-insulator NMOSFET featuring multiple stressors: silicon-carbon source/drain regions and tensile 124 stress silicon nitride liner,” IEEE Symposium on VLSI Technology Digest of Technical Papers,, pp 80-81, 2006 [87] G H Wang, E.-H Toh, K M Hoe, S Tripathy, S Balakumar, G.-Q Lo, G Samudra, and Y.-C Yeo, “Strained silicon-germanium-on-insulator n-MOSFETs featuring lattice mismatched source/drain stressor and high-stress silicon nitride liner,” Technical Dig International Electron Device Meeting, pp.469-472, 2006 [88] P Warren, J Mi, F Overney, M Dutoit, “Thermal stability of Si/Si1-x-yGexCy/Si heterostructures grown by rapid thermal chemical vapor deposition,” Journal of Crystal Growth, v 157, pp 414-419, 1995 [89] J W Strane, S T Picraux, H J Stein, S R Lee, and J Candelaria, “Stability and precipitation kinetics in Si1-yCy/Si and Si1-x-yGexCy/Si heterostructures prepared by solid phase epitaxy,” Mater Res Soc Symp Proc v 9415, 1993 [90] M Bauer, D Weeks, Y Zhang, V Machkaoutsan, “Tensile Strained Selective Silicon Carbon Alloys for Recessed Source Drain Areas of Devices,” ECS Transactions, v 3, no.7, pp 187-196, 2006 [91] M Berti De Salvador, A V Drigo, F Romanato, J Stangl, S Zerlauth, F Schäffler, and G Bauer, “Lattice parameter in Si1-yCy epilayers: deviation from Vegard's rule,” Appl Phys Lett., v 72, pp 1602-1604, 1998 [92] Y.-C Yeo and J Sun, Applied Physics Letters, v 86, pp 023103, 2005 [93] G H Wang, E.-H Toh, C.-H Tung, S Tripathy, G Samudra, and Y.-C Yeo, “Concept of strain-transfer-layer and integration with graded silicon-germanium source/drain stressors for p-type field effect transistor performance enhancement,” Japanese Journal of Applied Physics, v 46, no 4B, pp 2062-2066, 2008 125 [94] G H Wang, E H Toh, X Wang, S Tripathy, T Osipowicz, T K Chan, K M Hoe, S Balakumar, G Q Lo, G Samudra, Y.C Yeo, “Strained SiGeSn formed by Sn implant into SiGe and pulsed laser annealing”, Applied Physics Letters, v 91, no 20, pp 202105-1-3, 2007 [95] F J Guarin, S S Iyer, A R Powell, B A Ek, Applied Physics Letters, v 68, no 25, pp 3608, 1996 [96] J A Sharp, N E B Cowern, R P Webb, K J Kirkby, D Giubertoni, S Gennaro, M Bersani, M A Foad, F Cristiano, P F Fazzini, Applied Physics Letters, v 89, no.19, pp 2105, 2006 [97] Z Chen, F Zhang, J Chen, B Jin, Y Wang, C Zhang, Z Zhang, X Wang, Semiconductor Science and Technology, v 20, pp 770, 2005 [98] L Vegard, Zeitschrift for Physik A Hadrons and uclei, v 5, pp 17, 1921 [99] Kunihiro Suzuki, Hiroko Tashiro, Kazuko Narita, Yuji Kataoka, IEEE Trans Electron Device, v 51,no 5,pp 663, 2004 [100] P Kringho.j, A Nylandsted Larsen, and J W Petersen, Mater Res Soc.Symp Proc., v 163, pp 585 ,1990 [101] M R Sardela, R Turan, M Willander, G V Hansson, and L Hultman, J.Appl Phys., v 77, pp 1411, 1995 [102] G He and H A Atwater, Phys Rev Lett., v 79, pp 1937, 1997 [103] R Ragan and H A Atwater, Appl Phys Lett v 77,pp 3418, 2000 [104] D W Jenkins and J D Dow, Phys Rev B., v 36, pp 7994, 1987 [105] S I Shah, J E Green, L L Abels, Q Yao, and P M Raccah, J Cryst.Growth , v 83, pp 3, 1987 126 [106] J Piao, R Beresford, T Licata, I Wang, and H Homma, J Vac Sci Technol B, v 8, pp 221, 1990 [107] H Richter, Z P Wang, and L Ley, Solid State Commun, v 39, pp 625, 1981 [108] F Cerdeira, C J Buchenauer, F H Pollak, and M Cardona, Phys Rev B, v 5, pp 580, 1972 [109] O Madelung, Semiconductors—Basic Data, 2nd ed ~Springer, Berlin, pp 32 and 44, 1996 [110] J C Tsang, P M Mooney, F Dacol, and J O Chu, J Appl Phys v 75, pp 8098, 1994 [111] D Zhang, B Y Nguyen, T White, B Goolsby, T Nguyen, V Dhandapani, J Hildreth, M Foisy, V Adams, Y Shibo, A Thean, D Theodore, M Canonico, S Zollner, S Baichi, S Murphy, R Rai, J Jiang, M Jahanbani, R Nibble, M Zavala, R Cotton, D Eades, S Parsons, P Montogomery, A Martinez, B Winstead, M Medicino, J Cheek, J Liu, P Grudoswki, N Ramami, P Tomasinini, C Arena, C Werkhoven, H Kirby, C H Chang, C T Liu, H C Tuan, Y C See, S Vankatesan, V Kolagunta, N Cave and J Mogab, “Embedded SiGe S/D PMOS on thin body SOI substrate with drive current enhancement,” IEEE Symposium on VLSI Technology Digest of Technical Papers, pp 26-29, 2005 [112] M.Yoshimi, N Terauchi, A Nishiyama, O Arisumi, A Murakoshi, K Matsuzawa, N Shigyo, M Tomita, K Suzuki, Y Ushiku and H Tango, “Suppression of the floating body effect in SOI MOSFETS by the bandgap engineering method using a SiGe Source structure”, IEEE Trans Electron Devices, vol 44, no 3, p 423–430, 1997 127 [113] K C Liu, S K Ray, S K Oswal, and S K Banerjee, “A deep submicron SiGe/Si Vertical pMOSFET fabricated by Ge Ion Implantation”, IEEE Electron Devices Letters, vol 19, no 1, p 13–15, 1998 [114] R A Soref, C H Per, “Predicted band gap of the new semiconductor SiGeSn”, J Appl Phys., v 69, no 1, pp 539-541, 1991 [115] G H Wang, E.-H Toh, X Wang, S Tripathy, T Osipowicz, T K Chan, K.-M Hoe, S.Balakumar, G.-Q Lo, G Samudra, and Y.-C Yeo, "Strained SiGeSn formed by Sn implant into SiGe and pulsed laser annealing," Applied Physics Letters, vol 91, 2007 128 PUBLICATIO S [1] E.-H Toh, G H Wang, G.-Q Lo, N Balasubramanian, C.-H Tung, F Benistant, L Chan, G Samudra, and Y.-C Yeo, "A novel CMOS-compatible L-shaped Impact Ionization MOS (LI-MOS) transistor," IEEE International Electron Device Meeting 2005, Washington D.C., Dec 5-7, 2005, pp 971-974 [2] K.-J Chui, K.-W Ang, A Madan, G H Wang, C.-H Tung, L.-Y Wong, Y Wang, S.-F Choy, N Balasubramanian, M F Li, G Samudra, and Y.-C Yeo, "Source/drain germanium condensation for p-channel strained ultra-thin body transistors," IEEE International Electron Device Meeting 2005, Washington, D.C., Dec 5-7, 2005, pp 499-502 [3] G H Wang, E.-H Toh, Y.-L Lim, C.-H Tung, S.-F Choy, G S Samudra, and Y.-C Yeo, "High quality silicon-germanium-on-insulator wafers fabricated using cyclical thermal oxidation and annealing," Applied Physics Letters, vol 89, 053109, Aug 2006 [4] G H Wang, E.-H Toh, K.-W Ang, C.-H Tung, A Du, Y.-L Foo, G.-Q Lo, G Samudra, and Y.-C Yeo, "Strained SiGe-On-Insulator N-MOSFET with Silicon Source/Drain for Drive Current Enhancement," Extended Abstracts of the 2006 International Conferenceon Solid State Devices and Materials, Yokohama, Japan, Sep 13-15, 2006, pp 1048-1049 [5] E.-H Toh, G H Wang, L Chan, G.-Q Lo, G S Samudra, and Y.-C Yeo, "IMOS transistor with an elevated silicon-germanium impact-ionization region for bandgap engineering," IEEE Electron Device Letters, vol 27, no 12, pp 975-977, Dec 2006 129 [6] G H Wang, E.-H Toh, K M Hoe, S Tripathy, S Balakumar, G.-Q Lo, G Samudra, and Y.-C Yeo, "Strained silicon-germanium-on-insulator n-MOSFETs featuring lattice mismatched source/drain stressor and high-stress silicon nitride liner," IEEE International Electron Device Meeting 2006, San Francisco CA, Dec 11-13, 2006, pp 469-472 [7] E.-H Toh, G H Wang, G.-Q Lo, L Chan, G Samudra, and Y.-C Yeo, "Performance enhancement of n-channel impact-ionization MOS (I-MOS) transistor by strain engineering," Applied Physics Letters, vol 90, no 2, 023505, Jan 2007 [8] G H Wang, E.-H Toh, C.-H Tung, Y.-L Foo, S Tripathy, S Balakumar, G.-Q Lo, G Samudra, and Y.-C Yeo, "Fabrication of strain relaxed silicon-germaniumon-insulator (Si0.35Ge0.65OI) wafers using cyclical thermal oxidation and annealing," Materials Research Society Spring 2007 Meeting, San Francisco, CA, Apr 9-13, 2007 [9] G H Wang, E.-H Toh, K M Hoe, S Tripathy, S Balakumar, G.-Q Lo, G Samudra, and Y.-C Yeo, "Sub-50 nm strained n-FETs formed on silicongermanium-on-insulator substrates and the integration of silicon source/drain stressors," Materials Research Society Spring 2007 Meeting, San Francisco, CA, Apr 9-13, 2007 [10] G H Wang, E.-H Toh, C.-H Tung, Y.-L Foo, S Tripathy, S Balakumar, G.-Q Lo, G Samudra, and Y.-C Yeo, "Fabrication of strain relaxed silicon-germaniumon-insulator (Si0.35Ge0.65OI) wafers using cyclical thermal oxidation and annealing," Materials Research Society Proceedings 2007 130 [11] G H Wang, E.-H Toh, K M Hoe, S Tripathy, S Balakumar, G.-Q Lo, G Samudra,and Y.-C Yeo, "Sub-50 nm strained n-FETs formed on silicongermanium-on-insulator substrates and the integration of silicon source/drain stressors," Materials Research Society Spring Proceedings 2007 [12] E.-H Toh, G H Wang, G.-Q Lo, S.-F Choy, L Chan, G Samudra, and Y.-C Yeo, "A strained N-channel impact-ionization MOS (I-MOS) transistor with elevated silicon-carbon source/drain for performance enhancement," VLSI-TSA, Hsinchu, Taiwan, Apr 23-25, 2007, pp 86-87 [13] G H Wang, E.-H Toh, C.-H Tung, A Du, G.-Q Lo, G Samudra, and Y.-C Yeo, "Strained silicon-germanium-on-insulator n-channel transistor with silicon source and drain regions for performance enhancement," J.Journal of Applied Physics, vol 46, no 4B, pp 2062-2066, Apr 2007 [14] E.-H Toh, G H Wang, G Samudra, and Y.-C Yeo, "Device physics and design of double-gate tunneling field-effect-transistor by silicon film thickness optimization," Applied Physics Letters, vol 90, no 24, Jun 2007 [15] E.-H Toh, G H Wang, L Chan, G.-Q Lo, D Sylvester, C.-H Heng, G S Samudra, and Y.-C Yeo, "A Complementary-I-MOS Technology Featuring SiGe Channel and I-region For Enhancement of Impact-ionization, Breakdown Voltage, and Performance," 37th European Solid-State Device Research Conference (ESSDERC), Munich, Germany, Sep 11-13, 2007, pp 295-298 [16] G H Wang, E.-H Toh, Y.-L Foo, S Tripathy, S Balakumar, G.-Q Lo, G S Samudra, and Y.-C Yeo, "Uniaxial Strained Silicon n-FETs on SiliconGermanium-on-Insulator Substrates with an e-Si0.7Ge0.3 Stress Transfer Layer 131 and Source/Drain Stressors for performance enhancement," 37th European SolidState Device Research Conference (ESSDERC), Munich, Germany, Sep 11-13, 2007, pp 311-314 [17] G H Wang, E.-H Toh, C.-H Tung, S Tripathy, S Balakumar, G.-Q Lo, G Samudra, and Y.-C Yeo, "Silicon Strain-Transfer-Layer (STL) and graded source/drain stressors for enhancing the performance of silicon-germanium channel P-MOSFETs," Extended Abstracts of the 2007 International Conference on Solid State Devices and Materials, Ibaraki, Japan, Sep 18-21, 2007, pp 38-39 [18] G H Wang, E.-H Toh, C.-H Tung, S Tripathy, S Balakumar, G.-Q Lo, G Samudra, and Y.-C Yeo, "Silicon Strain-Transfer-Layer (STL) and graded source/drain stressors for enhancing the performance of silicon-germanium channel P-MOSFETs," Journal of Applied Physics 2008 [19] E.-H Toh, G H Wang, G.-Q Lo, L Chan, G Samudra, and Y.-C Yeo, "Doublespacer impact-ionization MOS transistor: Characterization and analysis," Extended Abstracts of the 2007 International Conference on Solid State Devices and Materials, Ibaraki, Japan, Sep 18-21, 2007, pp 208-209 [20] G H Wang, E.-H Toh, X.-C Wang, K.-M Hoe, S Tripathy, G.-Q Lo, G Samudra, and Y.-C Yeo, "Pulsed laser irradiation of silicon-germanium-oninsulator (Si0.17Ge0.83OI) substrates for strain relaxation and defect reduction," Extended Abstracts of the 2007 International Conference on Solid State Devices and Materials, Ibaraki, Japan, Sep 18-21, 2007, pp 290-291 [21] E.-H Toh, G H Wang, L Chan, D Sylvester, C.-H Heng, G Samudra, and Y.-C Yeo, "A double-gate tunneling field-effect transistor with silicon-germanium 132 source for high performance, low standby power, and low power technology applications," Extended Abstracts of the 2007 International Conference on Solid State Devices and Materials, Ibaraki, Japan, Sep 18-21, 2007, pp 894-895 [22] E.-H Toh, G H Wang, L Chan, G Samudra, and Y.-C Yeo, "Device Design and Scalability of an Impact-Ionization MOS Transistor with an Elevated Impact Ionization Region," 2007 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), Vienna, Austria, Sep 25-27, 2007, pp 129-132 [23] E.-H Toh, G H Wang, L Chan, G.-Q Lo, G Samudra, and Y.-C Yeo, "Strain and materials engineering of the I-MOS transistor with an elevated impactionization region," IEEE Trans Electron Devices, vol 54, no 10, pp 2778-2785, Oct 2007 [24] G H Wang, E.-H Toh, X Wang, S Tripathy, T Osipowicz, T K Chan, K.-M Hoe, S.Balakumar, G.-Q Lo, G Samudra, and Y.-C Yeo, "Strained SiGeSn formed by Sn implant into SiGe and pulsed laser annealing," Applied Physics Letters, vol 91, 2007 [25] G H Wang, E.-H Toh, A Du, G.-Q Lo, G Samudra, and Y.-C Yeo, "Strained silicongermanium- on-insulator N-MOSFET with embedded silicon source and drain stressors," IEEE Electron Device Letters, vol 28, 2008 [26] G H Wang, E.-H Toh, X Wang, D H.-L Seng, S Tripathy, T Osipowicz, T.-K Chan, K.-M Hoe, C.-H Tung, S Balakumar, G.-Q Lo, G S Samudra, and Y.-C Yeo, " Silicon- Germanium-Tin (SiGeSn) Source and Drain Stressors formed by Sn Implant and Laser Annealing for Strained Silicon-Germanium Channel P- 133 MOSFETs ," IEEE International Electron Device Meeting 2007, Washington, D.C., Dec 10-12, 2007 [27] E.-H Toh, G H Wang, M Zhu, C Shen, L Chan, G.-Q Lo, C.-H Tung, D Sylvester, C.-H Heng, G Samudra, and Y.-C Yeo, "Impact ionization nanowire transistor with multiple-gates, silicon-germanium impact ionization region, and sub-5 mV/decade subtheshold swing," IEEE International Electron Device Meeting 2007, Washington DC, Dec 10-12, 2007 [28] G H Wang, E.-H Toh, D Weeks, T Landin, J Spear, C H Tung, S G Thomas, G Samudra, and Y.-C Yeo, "Strained Si n-FET featuring compliant SiGe Stress Transfer Layer (STL) and Si0.98C0.02 Source/Drain Stressors for Performance Enhancement," International Semiconductor Device Research Symposium, College Park MD, USA, Dec.12-14, 2007 [29] G H Wang, E.-H Toh, R T P Lee, X.-C Wang, D H L Seng, S Tripathy, Y.L Foo, G Samudra, and Y.-C Yeo, "Contact technology for germanium-tin (GeSn) source/drain using nickel and nickel-platinum alloys," Materials Research Society Spring Meeting, Mar 24-28, 2008 [30] G H Wang, E.-H Toh, X.-C Wang, D K.-Y Low, S Tripathy, Y.-L Foo, G Samudra, and Y.-C Yeo, "Lattice compensation of Boron in Sn+ implanted Silicon-Germanium p+/n to achieve high quality strained SiGeSn upon pulsed laser annealing," Materials Research Society Spring Meeting, Mar 24-28, 2008 [31] G H Wang, E.-H Toh, T Osipowicz, T K Chan, Y.-L Foo, C H Tung, G Samudra, and Y.-C Yeo, "Strained silicon-germanium channel P-MOSFETs featuring Sn implanted silicon-germanium-tin (SiGeSn) source and drain stressors 134 formed by solid phase epitaxy," International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA), Hsinchu, Taiwan, Apr 21-23, 2008, pp 128-129 [32] G H Wang, E.-H Toh, X Wang, D H L Seng, S Tripathy, T Osipowicz, T K Chan, G Samudra, and Y.-C Yeo, "Performance enhancement schemes featuring lattice mismatched S/D stressors for CMOS: Embedded SiGeSn S/D for pFETs by Sn+ implant and SiC S/D for nFETs by C+ implant," Symp on VLSI Tech 2008, Honolulu HI, USA, Jun 17-19, 2008, pp 207-208 135 AWARDS ACCORDED [1] 2007 SSDM Young Researcher Award G H Wang, E.-H Toh, K.W Ang, C.-H Tung, A Du, Y.-L Foo, G.-Q Lo, G Samudra,and Y.-C Yeo, "Strained SiGe-On-Insulator NMOSFET with Silicon Source/Drain for Drive Current Enhancement," Extended Abstracts of the 2006 International Conference on Solid State Devices and Materials, Yokohama, Japan, Sep 13-15, 2006, pp 1048-1049 [2] 2008 BEST PAPER AWARD G H Wang, E.-H Toh, Y.-L Foo, S Tripathy, S Balakumar, G.-Q.Lo, G S Samudra,and Y.-C Yeo, "Uniaxial Strained Silicon n-FETs on Silicon-Germaniumon-Insulator Substrates with an e-Si0.7Ge0.3 Stress Transfer Layer and Source/Drain Stressors for performance enhancement," 37th European Solid-State Device Research Conference (ESSDERC), Munich, Germany, Sep 11-13, 2007, pp 311-314 [3] 2009 VLSI-TSA BEST PAPER AWARD Eng-Huat Toh, Grace Huiqi Wang, Doran Weeks, Ming Zhu, Trevan Landin, Jennifer Spear, Lap Chan, Shawn G Thomas, Ganesh Samudra, and Yee-Chia Yeo, P-Channel I-MOS 136 Transistor featuring Silicon Nano-Wire with Multiple-Gates, Si1-yCy I-region, in situ doped Si1-yCy Source, and Sub-5 mV/decade Subthreshold Swing” [4] 2005 A*Star Inaugural Conference Best Paper Award " Strained pFET featuring Ge Condensation in the Source Drain for enhanced performance" [5] 2008- Marquis Who's Who in the World 2009 [6] 2004- Academic Achievement Award 2007 [7] 2004- A*STAR Graduate Scholarship Award 2008 [8] 2003- A*STAR Pre-Graduate Scholarship Award 2004 137 “In the middle of difficulty lies opportunity.” Albert Einstein 138 ... p-FET performance i In summary, novel devices employing novel strain engineering techniques were studied They show promising potential for augmenting the performance of conventional CMOS transistors... describe to my daddy, my mummy and my lovely brother, Henry I thank them for their care and love in my entire life, and thank daddy and mummy for the sacrifices they have made and support throughout... and F At a gate overdrive of 1.0 V and VD of 1.0 V, IDsat enhancement of 15.3% and 59% were achieved for Devices D and F, respectively, over Device A (control) The effectiveness in the STL, and