[...]... background information on high- speed serial interface standards The chapter then enumerates the challenges that we are facing in high- speed serial interface testing, validation and debugging, and finally outlines our solutions to some of the most pressing challenges 1.1 Motivation The High Speed Serial Interface (HSSI), which is interchangeably referred to as Serializer/Deserializer (SerDes) or simply... architecture of the HSSI communication interfaces, together with its common applications Then, the bit error rate (BER) mechanisms are explained, and the jitter phenomenon is dealt with in detail Introduced are the relevant probabilistic properties and the basics of the simulation and emulation approaches to the modeling of BER effects 2.1 High- Speed Serial Communication The high- speed serial communication interfaces. .. in the data stream and a receiver employs specialized CDR circuitry to recover the data, as well as the clock While this recovery circuit is often used to name the whole communication system as a CDR, in this book, we prefer to refer to such a system as HSSI, as CDR block is just a part of the receiver Y Fan, Z Zilic, Accelerating Test, Validation and Debug of High Speed Serial Interfaces, DOI 10.1007/978-90-481-9398-1_2,... not have enough highspeed instruments to accommodate the testing of multi-lane HSSI devices The third challenge is jitter decomposition and jitter injection Many modern HSSI standards specify the jitter specifications in term of Deterministic Jitter (DJ) and Random Jitter (RJ), so the procedures for testing, characterization and validation as well need to be cognizant of such types of jitter 8 1 Introduction... concentrated on verifying that the device can work under all settings and can accommodate process variations allowed in manufacturing Characterization can in principle be done either in the lab or on Automatic Test Equipment (ATE), and there is a significant push to achieve Y Fan, Z Zilic, Accelerating Test, Validation and Debug of High Speed Serial Interfaces, DOI 10.1007/978-90-481-9398-1_1, © Springer Science+Business... cost control is one of the biggest challenges in a massproduction environment It is hence urgent to develop jitter testing techniques that can meet the cost requirement Fig 1-2 High speed serial interface technology trend The second major concern is the availability of high- speed instruments on an ATE tester The increasing bandwidth demand has been pushing the HSSI data rate higher and higher Figure 1-2... Block diagram of an HSSI The transmitter takes parallel data and converts it into a serial format The PLL in the transmitter generates an internal high- speed clock for the serializer to provide the synchronization mechanism for the outgoing serial data The differential line driver drives the serialized data into the transmission media The receiver, on the other hand, accepts the high- speed serial data... of three processes: validation of the first set of fabricated devices, characterization of the devices under all settings across Process, Voltage and Temperature (PVT) corners, and production testing Validation emphasizes on verifying complete device functionality, including parameter values and electrical characteristics Because of the increasing design complexity, close to 25% of all design resources... Overview of the Book In the remainder of the book, Chapter 2 presents the background of the research We first discuss the HSSI technologies and the BER mechanism BER is a measure of the HSSI overall performance We then introduce how the timing jitter and the amplitude noise can affect the BER performance In Chapter 3, the details of an ATE-based receiver testing solution are presented We use a high- speed. .. use for validation and characterization to shorten the time-to-market To validate, characterize and test HSSIs on ATE, there are several considerations that need to be addressed The first concern is the test cost In early days, HSSI devices were designed as high- performance and high- margin devices With the introduction of the low cost CMOS processes, most of the Gigahertz HSSIs are now built in high- volume . w0 h0" alt="" Accelerating Test, Validation and Debug of High Speed Serial Interfaces Yongquan Fan · Zeljko Zilic Accelerating Test, Validation and Debug of High Speed Serial Interfaces 123 ISBN. information on high- speed serial interface standards. The chapter then enumerates the challenges that we are facing in high- speed se- rial interface testing, validation and debugging, and finally. (ATE), and there is a significant push to achieve Y. Fan, Z. Zilic, Accelerating Test, Validation and Debug of High Speed Serial Interfaces, DOI 10.1007/978-90-481-9398-1_1, © Springer Science+Business