497 ❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚ ❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚ CHAPTER 11 Logic Gate Circuitry OUTLINE 11.1 Electrical Characteristics of Logic Gates 11.2 Propagation Delay 11.3 Fanout 11.4 Power Dissipation 11.5 Noise Margin 11.6 Interfacing TTL and CMOS Gates 11.7 Internal Circuitry of TTL Gates 11.8 Internal Circuitry of CMOS Gates 11.9 TTL and CMOS Variations CHAPTER OBJECTIVES Upon successful completion of this chapter, you will be able to: • Name the various logic families most commonly in use today and state several advantages and disadvantages of each. • Define propagation delay. • Calculate propagation delay of simple circuits, using data sheets. • Define fanout and calculate its value, using data sheets. • Calculate power dissipation of TTL and CMOS circuits. • Calculate noise margin of a logic gate from data sheets. • Draw circuits that will interface various CMOS and TTL gates. • Explain how a bipolar junction transistor can be used as a logic inverter. • Describe the function of a TTL input transistor in all possible input states: HIGH, LOW, and open-circuit. • Explain the operation of a totem pole output. • Illustrate how a totem pole output generates power line noise and describe how to remedy this problem. • Illustrate why totem pole outputs cannot be tied together. • Explain the difference between open-collector and totem pole outputs of a TTL gate. • Illustrate the operation of TTL open-collector inverter, NAND, and NOR gates. • Write the Boolean expression of a wired-AND circuit. • Design a circuit that uses an open-collector gate to drive a high-current load. • Calculate the value of a pull-up resistor at the output of an open-collector gate. • Explain the operation of a tristate gate and name several of its advantages. • Design a circuit using a tristate bus driver to direct the flow of data from one device to another. • Describe the basic structure of a MOSFET and state its bias voltage requirements. • Draw the circuit of an CMOS inverter and show how it works. 498 CHAPTER 11 • Logic Gate Circuitry • Draw the circuits of CMOS NAND and NOR gates and explain the operation of each. • Design a circuit using a CMOS transmission gate to enable and inhibit digital and ana- log signals. • Interpret TTL data sheets to distinguish between the various TTL families. • Describe the use of the Schottky barrier diode in TTL gates. • Calculate speed-power products from data sheets. O ur study of logic gates and flip-flops in previous chapters has concentrated on digital logic and has largely ignored digital electronics. Digital logic devices are electronic circuits with their own characteristic voltages and currents. No serious study of digital cir- cuitry is complete without some examination of this topic. It is particularly important to understand the inputs and outputs of logic devices as electronic circuits. Knowing the input and output voltages and currents of these circuits is essential, since gate loading, power dissipation, noise voltages, and interfacing between logic families depend on them. The switching speed of device outputs is also fundamental and may be a consideration when choosing the logic family for a circuit design. Input and output voltages of logic devices are specified in manufacturers’ data sheets, which allows us to take a “black box” approach initially. Later in the chapter, we will examine some basic digital circuits at a transistor level, since digital logic is based on transistor switching. Two major types of transistors, the bipo- lar junction transistor and the metal-oxide-semiconductor field effect transistor (MOSFET), form the basis of the major logic families in use today. Transistor-transistor logic (TTL) is based on the bipolar transistor. Complementary MOS (CMOS) is based on the MOSFET. We will briefly study the operating characteristics of both bipolar transistors and MOSFETs and then see how these devices give rise to the electrical characteristics of sim- ple logic gates. 11.1 Electrical Characteristics of Logic Gates TTL Transistor-transistor logic. A logic family based on bipolar transistors. CMOS Complementary metal-oxide semiconductor. A logic family based on metal-oxide-semiconductor field effect transistors (MOSFETs). ECL Emitter coupled logic. A high-speed logic family based on bipolar transistors. When we examine the electrical characteristics of logic circuits, we see them as practical, rather than ideal devices. We look at properties such as switching speed, power dissipation, noise immunity, and current-driving capability. There are several commonly available logic families in use today, each having a unique set of electrical characteristics that differ- entiates it from all the others. Each logic family gives superior performance in one or more of its electrical properties. CMOS consumes very little power, has excellent noise immunity, and can be used with a wide range of power supply voltages. TTL has a larger current-driving capability than CMOS. Its power consumption is higher than that of CMOS, and its power supply requirements are more rigid. ECL is fast, making it the choice for high-speed applications. It is inferior to CMOS and TTL in terms of noise immunity and power consumption. TTL and CMOS gates come in a wide range of subfamilies. Table 11.1 lists some of the TTL and CMOS variations of the quadruple 2-input NAND gate. All gates listed have KEY TERMS 11.1 • Electrical Characteristics of Logic Gates 499 the same logic function but different electrical characteristics. Other gates would be simi- larly designated, with the last two or three digits indicating the gate function (e.g., a quadruple 2-input NOR gate would be designated 74LS02, 74ALS02, 74F02, etc.). We will examine four electrical characteristics of TTL and CMOS circuits: propaga- tion delay, fanout, noise margin, and power dissipation. The first of these has to do with speed of output response to a change of input. The last three have to do with input and out- put voltages and currents. All four properties can be read directly from specifications given in a manufacturer’s data sheet or derived from these specifications. Figures 11.1 and 11.2 show how the input and output voltages and currents are defined in a 74XX00 NAND gate. This designation can be generalized to any logic gate input or output. Table 11.1 Part Numbers for a Quad 2-input NAND Gate in Different Logic Families Part Number Logic Family TTL 74LS00 Low-power Schottky TTL 74ALS00 Advanced low-power Schottky TTL 74F00 Fast TTL CMOS 74HC00 High-speed CMOS 74HCT00 High-speed CMOS (TTL-compatible inputs) 74LVX00 Low-voltage CMOS H H V IH L ϩ V OL ϩ L L V IL H ϩ Ϫ V OH ϩ Ϫ Ϫ Ϫ FIGURE 11.1 Input/Output Voltage Parameters H H I IH L I OL L L I IL H I OH FIGURE 11.2 Input/Output Current Parameters The voltages and currents are designated with two subscripts, one that designates an input or output and another that indicates the logic level. For example, V OL is the voltage at the gate output when the output is in the logic LOW state. I IL is the input current when the input is in the LOW state. These voltages and currents are specified in manufacturers’ published data sheets, which are usually available in print form in a data book or in an electronic format, such as Portable Document Format (pdf) on a CD or internet site. Figure 11.3 shows a data sheet for a 74LS00 NAND gate, which also shows parameter values for a 54LS00 device. A 54-series device is manufactured to military specifications, which require a high range of environmental operating conditions.A74-seriesdevice is suit- able for general or commercial use. We will limit ourselves to the 74-series devices. The voltage and current parameters indicated in Figures 11.1 and 11.2 are all shown in the 74LS00 data sheet. Some parameters are shown as typical values, as well as maximum or minimum. Typical values should be considered “information only” as device manufacturers 500 CHAPTER 11 • Logic Gate Circuitry FIGURE 11.3 74LS00 Data (1 of 2) Reprinted with permission of Motorola. QUAD 2-INPUT NAND GATE GUARANTEED OPERATING RANGES Symbol Parameter Min Typ Max Unit V CC Supply Voltage 54 74 4.5 4.75 5.0 5.0 5.5 5.25 V T A Operating Ambient Temperature Range 54 74 –55 0 25 25 125 70 °C I OH Output Current — High 54, 74 –0.4 mA I OL Output Current — Low 54 74 4.0 8.0 mA SN54/74LS00 QUAD 2-INPUT NAND GATE LOW POWER SCHOTTKY J SUFFIX CERAMIC CASE 632-08 N SUFFIX PLASTIC CASE 646-06 14 1 14 1 ORDERING INFORMATION SN54LSXXJ Ceramic SN74LSXXN Plastic SN74LSXXD SOIC 14 1 D SUFFIX SOIC CASE 751A-02 14 13 123456 12 11 10 9 V CC 8 7 GND • ESD > 3500 Volts 11.1 • Electrical Characteristics of Logic Gates 501 do not guarantee these values. An exception to this would be the supply voltage, V CC , whose typical value is simply indicated as the average of maximum and minimum values. Note that I IH and I IL are shown in Figure 11.2 as flowing in opposite directions, as are I OH and I OL . On a data sheet, a current entering a gate is indicated as positive and a current leaving the gate is shown as having a negative value. The reason for these current directions will become apparent when we examine the internal circuits of the gates later in the chapter. ❘❙❚ EXAMPLE 11.1 What is the maximum value of V OL for a 74LS00 NAND gate when the output current is at its maximum value? Solution When the output is in the LOW state, the output current is given by I OL , which has a maximum value of 8 mA. The output voltage, V OL , is specified for a value of 4 mA and for 8 mA. Since the output condition is specified for maximum I OL (8 mA), then V OL ϭ 0.5 V. ❘❙❚ FIGURE 11.3 74LS00 Data (2 of 2) Reprinted with permission of Motorola. SN54/74LS00 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol Parameter Min Typ Max Unit Test Conditions V IH Input HIGH Voltage 2.0 V Guaranteed Input HIGH Voltage for All Inputs V IL In p ut LOW Voltage 54 0.7 V Guaranteed Input LOW Voltage for V IL I npu t LOW V o lt age 74 0.8 V g All Inputs V IK Input Clamp Diode Voltage –0.65 –1.5 V V CC = MIN, I IN = –18 mA V OH Out p ut HIGH Voltage 54 2.5 3.5 V V CC = MIN, I OH = MAX, V IN = V IH V OH O u t pu t HIGH V o lt age 74 2.7 3.5 V CC OH IN IH or V IL per Truth Table V OL Out p ut LOW Voltage 54, 74 0.25 0.4 V I OL = 4.0 mA V CC = V CC MIN, V IN =V IL or V IH V OL O u t pu t LOW V o lt age 74 0.35 0.5 V I OL = 8.0 mA V IN = V IL or V IH per Truth Table I IH In p ut HIGH Current 20 µA V CC = MAX, V IN = 2.7 V I IH I npu t HIGH C urren t 0.1 mA V CC = MAX, V IN = 7.0 V I IL Input LOW Current –0.4 mA V CC = MAX, V IN = 0.4 V I OS Short Circuit Current (Note 1) –20 –100 mA V CC = MAX I CC Power Supply Current Total, Output HIGH 1.6 mA V CC = MAX CC Total, Output LOW 4.4 CC Note 1: Not more than one output should be shorted at a time, nor for more than 1 second. AC CHARACTERISTICS (T A = 25°C) Limits Symbol Parameter Min Typ Max Unit Test Conditions t PLH Turn-Off Delay, Input to Output 9.0 15 ns V CC = 5.0 V t PHL Turn-On Delay, Input to Output 10 15 ns CC C L = 15 pF 502 CHAPTER 11 • Logic Gate Circuitry The 74XX00 NAND gate data is sufficient to represent any logic functions having “normal” output current within its particular logic family. This data can be used for most gate or flip-flop circuits within the family. Some specialized devices with higher-current outputs (e.g., 74XX244 octal tristate buffers) have a different set of electrical characteris- tics within their family. In the following sections of the chapter, we will use a NAND gate from each of three device families (74LS00, 74HC00A, and 74HCT00A) for illustrating the general principles of the various electrical characteristics. Devices from other families will also be used in examples and problems. Data sheets for the various devices are included in Appendix C. ❘❙❚ SECTION 11.1 REVIEW PROBLEM 11.1 What are the maximum values of voltage and current we can expect at the output of a 74LS00 NAND gate when both inputs are LOW? 11.2 Propagation Delay t pHL Propagation delay when the device output is changing from HIGH to LOW. t pLH Propagation delay when the device output is changing from LOW to HIGH. Propagation delay occurs because the output of a logic gate or flip-flop cannot respond instantaneously to changes at its input. There is a short delay, on the order of several nanoseconds, between input change and output response. This is largely due to the charg- ing and discharging of capacitances inherent in the switching transistors of the gate or flip- flop. Figure 11.4 shows propagation delay in two gates: a 74XX00 NAND gate and a 74XX08 AND gate. Each gate has an identical input waveform, a LOW-HIGH-LOW pulse. After each input transition, the output changes after a short delay, t p . KEY TERMS FIGURE 11.4 Propagation Delay in NAND and AND Gates Two delays are shown for each gate: t pLH and t pHL . The LH and HL subscripts show the direction of change at the gate output; LH indicates that the output goes from LOW to HIGH, and HL shows the output changing from HIGH to LOW. Propagation delay is the time between input and output voltages passing through a standard reference value. The reference voltage for standard TTL is 1.5 V. LSTTL and CMOS have different reference voltages, as follows. 11.2 • Propagation Delay 503 Propagation Delay for Various Logic Families: LSTTL: Time from 1.3 V at input to 1.3 V at output. Other TTL: Time from 1.5 V at input to 1.5 V at output. CMOS: Time from 50% of maximum input to 50% of maximum output. ❘❙❚ EXAMPLE 11.2 Use the data sheet in Figure 11.3, as well as those in Appendix C, to find the maximum propagation delays for each of the following gates: 74LS00 (quadruple 2-input NAND), 74LS02 (quadruple 2-input NOR), 74LS08 (quadruple 2-input AND), and 74LS32 (quadruple 2-input OR). Solution NOTE Table 11.2 Propagation Delays of 74LS Gates 74LS00 74LS02 74LS08 74LS32 t pLH 15 ns 15 ns 15 ns 22 ns t pHL 15 ns 15 ns 20 ns 22 ns Table 11.2 shows the variation of propagation delay among logic gates of the same family (74LS TTL). Since each logic function has a different circuit, its propagation delay will differ from those of gates with different functions. ❘❙❚ EXAMPLE 11.3 Use data sheets to find the maximum propagation delays for each of the following logic gates: 74F00, 74AS00, 74ALS00, 74HC00, and 74HCT00. Solution Table 11.3 Propagation Delays of 74LS Gates 74F00* 74AS00 74ALS00 74HC00** 74HCT00*** t pLH 6 ns 4.5 ns 11 ns 15 ns 19 ns t pHL 5.3 ns 4 ns 8 ns 15 ns 19 ns *Temperature range (74F00): 0°C to 70°C. **V CC ϭ 4.5 V, temperature range (74HC00): Ϫ55°C to 25°C. ***V CC ϭ 5 V, temperature range (74HCT00): Ϫ55°C to 25°C. As indicated by the notes for Table 11.3, propagation delay (and other parameters) vary with certain operating conditions, such as ambient temperature and power supply voltage. Always make sure that the operating conditions are correctly specified when look- ing up a data sheet parameter. ❘❙❚ All gates in Example 11.3 have the same logic function (2-input NAND), but differ- ent propagation delay times. We might ask, “Why not always use the advanced Schottky TTL gate (74AS00), since it is the fastest?” The main reason is that it has the highest power dissipation of the gates shown. We wouldn’t know this without looking up other specs on the data sheet. (We will learn how to do this later in the chapter.) Thus, it is important to make design decisions based on complete information, not just one parameter. 504 CHAPTER 11 • Logic Gate Circuitry Propagation Delay in Logic Circuits A circuit consisting of two or more gates or flip-flops has a propagation delay that is the sum of delays in the input-to-output path. Delays in gates that do not affect the circuit output are disregarded. Figure 11.5 shows how propagation delay works in a simple logic circuit consisting of a 74HC08 AND gate and a 74HC32 OR gate. Changes at inputs A and B must propagate through both gates to affect the output. The total delay in such a case is the sum of t p1 and t p2 . A change at input C must pass only through gate 2. The circuit delay resulting from this change is only t p2 . FIGURE 11.5 Propagation Delays in a Logic Gate Circuit The timing diagram in Figure 11.5 shows the changes at inputs A, B, and C and the re- sulting transitions at all gate outputs. Assume V CC ϭ 4.5 V and temperature range is Ϫ55°C to 25°C. 1. When A goes LOW, AB, the output of gate 1, also goes LOW after a maximum delay of t pHL ϭ 15 ns. This makes Y go LOW after a further delay of up to t pHL ϭ 15 ns. Total delay: t p ϭ t pHL1 ϩ t pHL2 ϭ 15 ns ϩ 15 ns ϭ 30 ns, max. 2. The HIGH-to-LOW transition at input B has no effect, since there is no difference be- tween 0 и 1 and 0 и 0. AB is already LOW. 3. The LOW-to-HIGH transition at input C makes Y go HIGH after a maximum delay of t pLH2 ϭ 15 ns. ❘❙❚ SECTION 11.2 REVIEW PROBLEM 11.2 Assume the gates in Figure 11.5 are replaced by a 74LS08 AND gate and a 74LS32 OR gate. Repeat the calculations of for the propagation delays if the waveforms of Figure 11.5 are applied to the circuit. The data sheets for the 74LS08 and 74LS32 are found in Appendix C. 11.3 • Fanout 505 11.3 Fanout Fanout The number of load gates that a logic gate output is capable of driving without possible logic errors. Driving gate A gate whose output supplies current to the inputs of other gates. Load gate A gate whose input current is supplied by the output of another gate. Sourcing A terminal on a gate or flip-flop is sourcing current when the current flows out of the terminal. Sinking A terminal on a gate or flip-flop is sinking current when the current flows into the terminal. I OL Current measured at a device output when the output is LOW. I OH Current measured at a device output when the output is HIGH. I IL Current measured at a device input when the input is LOW. I IH Current measured at a device input when the input is HIGH. We have assumed that logic gates are able to drive any number of other logic gates. Since gates are electrical devices with finite current-driving capabilities, this is obviously not the case. The number of gates (“loads”) a logic gate can drive is referred to as its fanout. Fanout is simply an application of Kirchhoff’s current law: The algebraic sum of currents at a node must be zero. Thus, the fanout of a logic gate is limited by: a. The maximum current its output can supply safely in a given logic state (I OH or I OL ), and b. The current requirements of the load to which it is connected (I IH or I IL ). Figure 11.6 shows the fanout of an AND gate when its output is in the HIGH and LOW states. The AND gate, or driving gate, supplies current to the inputs of the other four gates, which are called the load gates. Each load gate requires a fixed amount of input current, depending on which state it is in. The sum of these input currents equals the current supplied by the driving gate. The NOTE KEY TERMS FIGURE 11.6 Driving Gates and Load Gates 506 CHAPTER 11 • Logic Gate Circuitry fanout is determined by the amount of current the driving gate can supply without damag- ing its output circuit. The input and output currents of a gate are established by its internal circuitry. These values are usually the same for two gates in the same family, since the input and output cir- cuitry of a gate is common to all members of the family. Exceptions may occur when the output of a particular gate, such as the 74XX244 octal three-state buffer, has additional out- put buffering or an input of a gate such as a 74LS86 Exclusive OR is equivalent to more than one input load. ❘❙❚ EXAMPLE 11.4 The gates in Figure 11.7a and b are 74LS00 NAND gates. Determine the output current of the driving gate in each figure. H H I OL L I IL L L I OH H I IH a. Low output on driving gate b. High output on driving gate FIGURE 11.7 Example 11.4 Output Current due to One Load Gate Solution From the 74LS00 data sheet, I IL ϭϪ0.4 mA and I IH ϭ 20 ␮A. (There are two values of I IH given in the data sheet. Choose the one for the condition V IN ϭ 2.7 V, which is the minimum output voltage of a driving gate in the HIGH state (V OH ). The other value is not appropriate since a gate will never have a 7 V output, as specified in the condition, if its supply voltage is 5 V.) Since the driving gate is driving one load, its output current is the same as the input current of the load gate. Therefore, the driving gate output currents are given by I OL ϭ 0.4 mA (positive, since it is entering the driving gate output) and I OH ϭϪ20 ␮A (negative, since it is leaving the driving gate output). ❘❙❚ EXAMPLE 11.5 Determine the output current of the driving gate in each of Figures 11.8a and b if the gates are all 74LS00 NAND gates. H H I OL L I IL I IL a. Low output on driving gate L L I OH H I IH I IH b. High output on driving gate FIGURE 11.8 Example 11.5 Output Current due to Two Load Gates [...]... at least two types of logic gate AND and NOR The wired -AND configuration can synthesize any size of AND- OR-INVERT network using only NAND gates The wired -AND function is sometimes shown as an AND symbol around a soldered connection, as shown in Figure 11. 31b 11. 7 • Internal Circuitry of TTL Gates 529 FIGURE 11. 31 NAND Gates in Wired -AND Connection High-Current Driver Standard TTL outputs have higher... also used Wired -AND NOTE A wired -AND connection combines the outputs of the connected gates in an AND function FIGURE 11. 28 Open-Collector Symbols Shown for a NAND Gate (e.g., 7401) FIGURE 11. 29 Three Inverters in a Wired -AND Connection Figure 11. 29 shows three open-collector inverters connected in a wired -AND configuration The output transistors of the inverters are shown in Figure 11. 30, with different... that the LOW- and HIGH-state output transistors of a totem pole output are always in opposite phase (i.e., one ON, one OFF) Figure 11. 34 shows one gate of a 7400 quadruple 2-input NAND with totem pole outputs The circuit is the same as that for a 7401 open-collector NAND except for a transistor, resistor, and diode, which make up the HIGH-state output circuitry of the NAND gate FIGURE 11. 34 NAND Gate... connection is sometimes called “wired-OR.” Figure 11. 31 shows three NAND gates in a wired -AND connection Since the output functions are ANDed, the Boolean expression for Y is: Y ϭ ෆ и CD и ෆ AB ෆ EF ϭ AB ϩ CD ϩ EF 528 C H A P T E R 1 1 • Logic Gate Circuitry FIGURE 11. 30 Output Transistors of OpenCollector Inverters in a WiredAND Connection The resulting function is called AND- OR-INVERT Normally this requires... inputs HIGH make the output LOW FIGURE 11. 27 DeMorgan Equivalent Forms of a NAND Gate ❘❙❚ SECTION 11. 7A REVIEW PROBLEM 11. 7 What are the two main functions of the pull-up resistor on the output of an opencollector gate? Open-Collector Applications KEY TERM Wired -AND A connection where open-collector outputs of logic gates are wired together The logical effect is the ANDing of connected functions A more... driving low-voltage CMOS 11. 6 • Interfacing TTL and CMOS Gates 517 High-Speed CMOS driving 74LS To design an interface between any two logic families, we must examine the output voltages and currents of the driving gate and the input voltages and currents of the load gates Assume a 74HC00 NAND gate drives one or more 74LS00 NAND gates From the 74HC00 data sheet, we determine that VOH ϭ 3.98 V and VOL... common in TTL circuits and can be modeled by the diode equivalent in Figure 11. 25b Figure 11. 26 shows the response of the multiple-emitter input transistor to various combinations of logic levels 11. 7 • Internal Circuitry of TTL Gates 525 FIGURE 11. 25 TTL NAND with Open Collector Output FIGURE 11. 26 Input Response of Multiple-Emitter Transistor If both inputs are LOW, the NAND acts exactly the same... cycle ❘❙❚ EXAMPLE 11. 8 Figure 11. 12 shows a circuit constructed from the gates in a 74XX00 quadruple 2-input NAND gate package Use the data sheet shown in Figure 11. 3 to determine the maximum power dissipation of the circuit if the input is DCBA ϭ 1001 and the gates are 74LS00 NANDs Refer to the data sheets in Appendix C and repeat the calculation for 74ALS00 and 74AS00 gates FIGURE 11. 12 Power Dissipation... reasons: its output is only designed to withstand 5.5 V and it can only sink a maximum of 8 mA ❘❙❚ Value of External Pull-up Resistor The value of the pull-up resistor required by an open-collector circuit is calculated using manufacturer’s specifications and the basic principles of circuit theory: Kirchhoff’s voltage and current laws (KVL and KCL) and Ohm’s law Figure 11. 33 shows the circuit model for calculating... characteristic range of values for the power it consumes For TTL and CMOS, the power dissipation is calculated as follows: TTL: High-Speed CMOS: PD ϭ VCC ICC PD ϭ VCC IT (IT ϭ quiescent ϩ dynamic supply current) Figure 11. 11 shows the supply voltage and current in a 74XX00 NAND gate FIGURE 11. 11 Power Supply Voltage and Current in a 74XX00 NAND gate Vcc Icc Icc The main difference between the two families . 497 ❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚ ❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚ CHAPTER 11 Logic Gate Circuitry OUTLINE 11. 1 Electrical Characteristics of Logic Gates 11. 2 Propagation Delay 11. 3 Fanout 11. 4 Power Dissipation 11. 5 Noise Margin 11. 6 Interfacing TTL and CMOS. open-collector and totem pole outputs of a TTL gate. • Illustrate the operation of TTL open-collector inverter, NAND, and NOR gates. • Write the Boolean expression of a wired -AND circuit. • Design. Calculate speed-power products from data sheets. O ur study of logic gates and flip-flops in previous chapters has concentrated on digital logic and has largely ignored digital electronics. Digital logic