Introduction to Electronics 230 MOSFET Logic Inverters V DD V I V O R pull-up Fig. 306. NMOS inverter with resistive pull-up for the load. Drain Voltage, V DS V GS = 3 V V GS = 4 V V GS = 5 V V GS = 6 V 8 V V GS = 7 V 9 10 V Fig. 307. Ideal FET output characteristics, and load line for V DD = 10 V and R pull-up = 10 k Ω . Drain Current, I D MOSFET Logic Inverters NMOS Inverter with Resistive Pull-Up As Fig. 306 shows, this is the most basic of inverter circuits. Circuit Operation: The term NMOS implies an n -channel enhancement MOSFET. Using a graphical analysis technique, we can plot the load line on the output characteristics, shown below. When the FET is operating in its triode region, it pulls the output voltage low, i.e., toward zero. When the FET is in cutoff, the drain resistance pulls the output voltage up , i.e., toward V CC , which is why it is called a pull-up resistor . Because V GS = V I and V DS = V O , we can use Fig. 307 to plot the transfer function of this inverter. Introduction to Electronics 231 MOSFET Logic Inverters Input Voltage, V I Fig. 308. Inverter transfer function. Drawbacks: 1. A large R results in reduced V O for anything but the largest loads, and slows output changes for capacitive loads. 2. A small R results in excessive current, and power dissipation, when the output is low. The solution to both of these problems is to replace the pull-up resistor with an active pull-up . Output Voltage, V O Introduction to Electronics 232 MOSFET Logic Inverters V DD V I V O D D S S G G v GSN v SGP + + + - - - v SDP v DSN + - Fig. 309. CMOS inverter. Drain-Source Voltage of NMOS FET, V DSN V GSN = 3 V V GSN = 4 V V GSN = 5 V V GSN = 6 V V GSN = 7 V 8 V10 V 9 Fig. 310. Ideal NMOS output characteristics. Drain Current, I D CMOS Inverter Circuit Operation: The CMOS inverter uses an active pull-up , a PMOS FET in place of the resistor. The PMOS and NMOS devices are complementary MOSFETs, which gives rise to the name CMOS . In the previous example, the resistor places a load line on the NMOS output characteristic. Here, the PMOS FET places a load curve on the output characteristic. The load curve changes as V I changes !!! The NMOS output curves are the usual fare, and are shown in the figure below: Introduction to Electronics 233 MOSFET Logic Inverters V SGP = 3 V V SGP = 4 V V SGP = 5 V V SGP = 6 V V SGP = 7 V 8 V10 V 9 Source-Drain Voltage of PMOS FET, V SDP Fig. 311. Ideal PMOS output characteristics. vVv SGP DD GSN =− (339) vVv SDP DD DSN =− (340) Drain Current, | I D | The PMOS output curves, above, are typical also, but on the input side of the PMOS FET: This means we can re-label the PMOS curves in terms of v GSN . And, on the output side of the PMOS FET: This means we can “rotate and shift” the curves to display them in terms of v DSN . This is done on the following page. Introduction to Electronics 234 MOSFET Logic Inverters V DSN (= 10 V - V SDP ) V GSN = 7 V ( V SGP = 3 V) V GSN = 6 V ( V SGP = 4 V) V GSN = 5 V ( V SGP = 5 V) V GSN = 4 V ( V SGP = 6 V) V GSN = 3 V 2 V 0 V 1 Fig. 312. PMOS “load curves” for V DD = 10 V. Drain Current, | I D | The curves above are the same PMOS output characteristics of Fig. 233, but they’ve been: 1. Re-labeled in terms of v GSN . 2. Rotated about the origin and shifted to the right by 10 V (i.e., displayed on the v DSN axis). Introduction to Electronics 235 MOSFET Logic Inverters V GSN = 7 V V GSN = 6 V V GSN = 5 V V GSN = 4 V V GSN = 3 V 2 V 0 V 1 V GSN = 3 V V GSN = 4 V V GSN = 5 V V GSN = 6 V V GSN = 7 V8 V10 V 9 NMOS Drain-Source Voltage, V DSN Fig. 313. NMOS output characteristics (in blue) and PMOS load curves (in green) plotted on same set of axes. Drain Current, | I D | We can now proceed with a graphical analysis to develop the transfer characteristic. We do so in the following manner: 1. We plot the NMOS output characteristics of Fig. 310, and the PMOS load curves of Fig. 312, on the same set of axes. 2. We choose the single correct output characteristic and the single correct load curve for each of several values of v I . 3. We determine the output voltage from the intersection of the output characteristic and the load curve, for each value of v I chosen in the previous step. 4. We plot the v O vs. v I transfer function using the output voltages determined in step 3. The figure below shows the NMOS output characteristics and the PMOS load curves plotted on the same set of axes: Introduction to Electronics 236 MOSFET Logic Inverters NMOS Drain-Source Voltage, V DSN V I = V GSN = 3 V Fig. 314. Appropriate NMOS and PMOS curves for v I = 3 V. V I = V GSN = 4 V NMOS Drain-Source Voltage, V DSN Fig. 315. Appropriate NMOS and PMOS curves for v I = 4 V. Drain Current, | I D | Drain Current, | I D | Note from Fig. 313 That for V I = V GSN 2 V the NMOS FET (blue ≤ curves) is in cutoff, so the intersection of the appropriate NMOS and PMOS curves is at V O = V DSN = 10 V. As V I increases above 2 V, we select the appropriate NMOS and PMOS curve, as shown in the figures below. Introduction to Electronics 237 MOSFET Logic Inverters V I = V GSN = 5 V NMOS Drain-Source Voltage, V DSN Fig. 316. Appropriate NMOS and PMOS curves for v I = 5 V. V I = V GSN = 6 V NMOS Drain-Source Voltage, V DSN Fig. 317. Appropriate NMOS and PMOS curves for v I = 6 V. Drain Current, | I D | Drain Current, | I D | Because the ideal characteristics shown in these figures are horizontal, the intersection of the two curves for V I = V GSN = 5 V appears ambiguous, as can be seen below. However, real MOSFETs have finite drain resistance, thus the curves will have an upward slope. Because the NMOS and PMOS devices are complementary, their curves are symmetrical, and the true intersection is precisely in the middle: Introduction to Electronics 238 MOSFET Logic Inverters Input Voltage, V I Fig. 319. CMOS inverter transfer function. Note the similarity to the ideal transfer function of Fig. 298. NMOS Drain-Source Voltage, V DSN V I = V GSN = 7 V Fig. 318. Appropriate NMOS and PMOS curves for v I = 7 V. Output Voltage, V O For V I = V GSN 8 V, the PMOS FET (green curves) is in cutoff, so ≥ the intersection is at V O = V DSN = 0 V. Collecting “all” the intersection points from Figs. 314-318 (and the ones for other values of v I that aren’t shown here) allows us to plot the CMOS inverter transfer function : Drain Current, | I D | Introduction to Electronics 239 Differential Amplifier + - + - + - + - v I1 v I2 v ICM v ID /2 v ID /2 1 1 2 2 +- Fig. 320. Representing two sources by their differential and common-mode components (Fig. 41 repeated). vv v vv v IICM ID IICM ID 12 22 =+ =− and (341) vvv v vv ID I I ICM II =− = + 12 12 2 and (342) Differential Amplifier We first need to remind ourselves of a fundamental way of representing any two signal sources by their differential and common-mode components. This material is repeated from pp. 27- 28: Modeling Differential and Common-Mode Signals As shown above, any two signals can be modeled by a differential component, v ID , and a common-mode component, v ICM , if : Solving these simultaneous equations for v ID and v ICM : Note that the differential voltage v ID is the difference between the signals v I1 and v I2 , while the common-mode voltage v ICM is the average of the two (a measure of how they are similar). [...]... previously: -VEE Fig 328 Differential amplifier (Fig 321 repeated) RC RC + vo1 - ib1 + vod - + vo2 - ib2 - + vid /2 - βib2 βib1 rπ rπ vid /2 + vX (β+1)ib1 (β+1)ib2 REB Fig 3 29 Small-signal equivalent with a differential input REB is the equivalent ac resistance of the bias current source Small-Signal Analysis of Differential Amplifier Introduction to Electronics RC RC + vo1 - ib1 247 + vod - + vo2 - ib2 - +... RC + vo1 - ib1 + vod - + vo2 - ib2 + + vicm - βib1 rπ βib2 rπ vicm - (β+1)ib1 2REB (β+1)ib2 2REB Fig 335 Small-signal equivalent with a common-mode input The resistance of the bias current source is represented by 2REB || 2REB = REB Small-Signal Analysis of Differential Amplifier Introduction to Electronics RC RC + vo1 - ib1 + vod - + vo2 - ib2 + + vicm - 252 βib2 βib1 rπ rπ vicm - iX = 0 (β+1)ib1 2REB... where the subscript b refers to a balanced output Thus, we can refer to differential gain for either a single-ended output or a differential output Small-Signal Analysis of Differential Amplifier Introduction to Electronics RC RC + vo1 - ib1 + vod - + vo2 - ib2 - + vid /2 - 250 βib2 βib1 rπ rπ vid /2 + vX (β+1)ib1 (β+1)ib2 REB Fig 333 Diff amp small-signal equivalent (Fig 3 29 repeated) Remember our hyperbolic... −αRC IBIAS -1 V - iC1 241 Introduction to Electronics This is a mirror image of Case #2A We have vID = -2 V and vICM = 0 RC + vOD + + vO1 vO2 - iC2 Q2 Now Q2 is active and Q1 cutoff: +1 V + 0.7 V - vID /2 = -1 V (353) - IBIAS iC1 = 0 v O1 = VCC (354) + + 0.3 V iC 2 = αi E 2 = αIBIAS (355) v O 2 = VCC − αRC IBIAS (356) v OD = αRC IBIAS (357) vID /2 = -1 V -VEE Fig 324 Differential amplifier with -2 V differential... decouples the left half-circuit from the right half-circuit Again we need only analyze one-half of the circuit !!! Small-Signal Analysis of Differential Amplifier Introduction to Electronics 253 Analysis of Common-Mode Half-Circuit RC + vo1 or vo2 - ib1 + vicm - βib1 rπ 2REB Fig 337 Either half-circuit of diff amp with a common-mode input Again, the circuit at left is just the small-signal equivalent of... collect terms: − − [ ] [ v id = i b 2 rπ + (β + 1)REB + i b1 (β + 1)REB 2 (371) ] (372) Small-Signal Analysis of Differential Amplifier Introduction to Electronics RC RC + vo1 - ib1 + vod - + vo2 - ib2 - + vid /2 - 248 βib2 βib1 rπ rπ vid /2 + vX (β+1)ib1 (β+1)ib2 REB Fig 331 Diff amp small-signal equivalent (Fig 3 29 repeated) Adding (370) and (372): [ 0 = (i b1 + i b 2 ) rπ + 2(β + 1)REB ] (373) Because...Differential Amplifier Introduction to Electronics 240 Basic Differential Amplifier Circuit VCC The basic diff amp circuit consists of two emitter-coupled transistors RC RC + vOD - + vO1 - iC1 + vO2 - Q1 vI1 We can describe the total instantaneous output voltages: iC2 v O1 = VCC − RC iC1 Q2 vI2 And the total instantaneous differential output voltage: IBIAS v OD = v O1 − v O 2 -VEE = RC (iC 2 − iC1)... Q1 0.7 V - + vID /2 = 1 V + vOD + + vO1 vO2 Q2 0.3 V Now we let vID = 2 V and vICM = 0 iC2 RC iC1 Note that Q1 is active, but Q2 is cutoff Thus we have: iC2 = 0 + -1 .3 V - IBIAS vID /2 = 1 V + -VEE Fig 323 Differential amplifier with +2 V differential input RC + Q1 -1 .3 V - v O 2 = VCC (3 49) iC1 = αi E 1 = αIBIAS (350) v O1 = VCC − αRC IBIAS (351) (352) Case #2B - Differential Input: VCC -1 V (348)... VT Fig 326 Normalized collector currents vs normalized differential input voltage, for a differential amplifier Note that IBIAS is steered from one side to the other as vid changes from approximately -4 VT (-1 00 mV) to +4VT (+100 mV)!!! Large-Signal Analysis of Differential Amplifier Introduction to Electronics 244 Using (363) and (364), and recalling that vOD = RC ( iC2 - iC1 ):    v   v ... signal ground for all values of REB !!! The junction between the collector resistors is also at signal ground, so the left half-circuit and the right half-circuit are independent of each other, and can be analyzed separately !!! Small-Signal Analysis of Differential Amplifier 2 49 Introduction to Electronics Analysis of Differential Half-Circuit The circuit at left is just the smallsignal equivalent of . V v ID /2 = -1 V + + - - -1 V +1 V 0.7 V + - 0.3 V -1 .3 V + - Fig. 324. Differential amplifier with -2 V differential input. i C 2 0 = (348) vV OCC 2 = (3 49) iiI C E BIAS 11 == αα (350) vV. can write: and Introduction to Electronics 241 Differential Amplifier R C R C I BIAS V CC -V EE v OD v O1 v O2 Q 1 Q 2 i C1 i C2 + + + - v ID /2 = 1 V v ID /2 = 1 V + + - - +1 V -1 V 0.7 . dissipation, when the output is low. The solution to both of these problems is to replace the pull-up resistor with an active pull-up . Output Voltage, V O Introduction to Electronics 232 MOSFET Logic Inverters V DD V I V O D D S S G G v GSN v SGP + + + - - - v SDP v DSN + - Fig.