416 9 Data Acquisition and Model Parameter Measurements I TEST SIGNAL - GROUND HP4275A LCR METER - Fig. 9.9 Block diagram of an HP4275A LCR meter. The ‘Lo’ and ‘Hi’ terminals are connected to device under test whose capacitance is to be measured (H,) as shown in Figure 9.9. It has an internal DC bias voltage which is supplied from the H, terminal; H, is only for monitoring voltages and is kept in a high impedance state. The LCR meter monitors L, and keeps its potential equal to the ground level by controlling the current into the L, terminal. Since L, is always at ground level, there is no charge-discharge current due to the wiring capacitance or any other floating capacitances. The meter has a resolution of 0.1 fF [9]. While measuring capacitance it may become necessary to correct the capacitance meter reading for the parasitic capacitance and inductance of the test fixture. Electrically, the test fixture (chuck, probes, and cables) can be represented by three parasitic capacitances as shown in Figure 9.10a. C, and C, are the stray and wiring capacitances to ground associated with the probe and the chuck, respectively. As mentioned earlier these capaci- tances are ignored by three and four terminal capacitance meters. The capacitance C, between the chuck and the probe, for two terminal devices such as MOS capacitor, can be reduced to less than 0.01pF by proper grounding and shielding (cf. section 9.1, low current measurement consi- derations). However, for three or four terminal devices such as MOSFET, C, is the sum of (1) the capacitance C,, between the polysilicon gate line and the metal lines of the source and the drain contacts (pads), and (2) the interprobe capacitance Cip, so that C, = C,, + Ci, (see Figure 9.10b). The gate-source or gate-drain line parasitic capacitance C,, is fixed and 9.1 Data Acquisition 417 (b) Fig. 9.10 Schematic showing capacitances associated with the test fixture and device under test (DUT) for capacitance measurements of (a) an MOS capacitor, (b) an MOSFET. independent of the terminal voltages. Generally, test structures are used that minimize C,,,,. The interprobe capacitance Ci, is minimized using coaxial probes so that the gate electrode is shielded from the drain/source probes. Though Ci, can be reduced to 4-5fF using coaxial probes, compared to a few pF for ordinary probes, it cannot be made zero. This is because the tip of the probe, where most stray capacitance is picked up, is not shielded; the smaller the unshielded portion of the tip, the smaller the interprobe capacitances. In practice it is possible to effectively zero out the interprobe capacitance Ci, by subtracting the open circuit capacitance. The series inductance is due to the loop of the feed wire that connects the probe and the chuck to the inner conductors of the cables. Typically, its value lies between 20 nH and 200 nH. This inductance is important only if one needs accurately the impedance of the capacitance structure. The efSect of stray capacitances and inductances is minimized by keeping the connecting cables short, no more than a foot, as it adds up capacitance to ground. 418 9 Data Acquisition and Model Parameter Measurements t I I I I During MOSFET capacitance measurements, often several DC bias volt- ages are applied to the device terminals. Since these voltages are provided by separate power supplies, it is essential that ground terminals of all equipments be connected together. Otherwise, any difference (typically a few mV) in the ground potentials of different equipment will appear on the device terminal which is unaccounted for. Further, in order to avoid any AC signal flowing into the power supplies, large capacitors (typically 1 pF) are connected across the terminals of the power supplies to bypass the AC signals to ground. I I 0 9.1.3 MOS Capacitor C-V Measurement 0 I As was pointed out in section 4.6, the MOS capacitor as a test device is routinely used to measure low frequency (LF) and high frequency (HF) C-V curves for MOS process and device characterization. We will now discuss the experimental setup for measuring these curves [l], [13], [lS]. X-Y RECORDER Low Frequency C-V Measurement. The low frequency C-V curve requires a frequency as low as 1 Hz, which is difficult to achieve experimentally. Therefore, in practice an alternative method, called the quasi-static technique, is often used [17], [l, pp. 383-3891. In this technique, the displacement current through the MOS capacitor is measured. In this respect this method is slightly different from normal AC capacitance measurements. Figure 9.1 1 shows a block diagram of the setup for an LF C-V measurement. The MOS capacitor to be measured is connected to a linear voltage ramp generator and a sensitive current meter (an electrometer or a picoAmmeter I I -I - I 112 HP4140B ; I :DEVICE : I ' UNDER : 1/2 HP4140B : I IcHucKI TEST I L - - - - - - - - -1 I 0 I I -4Y ox Cr == i -' 0 I- 1- Fig. 9.11 Block diagram of the quasi-static C-V measurement setup 9.1 Data Acquisition 419 such as the HP4140B). The voltage output of the ramp generator can be expressed as V=V,+rt (9.3) where V, is the voltage at t = 0 and r = dV/dt is the ramp rate. Due to the varying ramp voltage, a displacement current i flows in the capacitor dQ dQ dV dt dV dt -=CC,r (A) i=-= (9.4) measured by the current meter, and is directly proportional to the capaci- tance C, of the MOS capacitor. Since there is no AC signal involved, the capacitance corresponds to the limiting case of zero frequency. The ramp rate r should be sufficiently slow to maintain equilibrium conditions in the interface state charge and minority carrier distribution. However, it must be fast enough so that the signal-to-noise ratio is as high as possible. Experimentation is generally necessary to obtain the optimum ramp rate. Typical values of the ramp rate used are 10-100 mV/s. This implies that for a capacitor of 100 pF, the (displacement) current is somewhere between 10 pA to 0.1 PA. The ramp generator should exhibit linearity better than 1% in order to reach an accuracy of 1% in the measurement. To measure these low currents, the method of interconnection, grounding and shielding are of great importance (cf. section 9.1). The HP 4140B serves a dual purpose as it contains both an ultralinear ramp voltage generator and a picoAmmeter with resolution down to 0.01 PA. The filter capacitor C, suppresses the noise (voltage spike) of the ramp generator; it is composed of a non-polar electrolytic capacitor and a small ceramic disc capacitor for shunting higher frequencies. The quasi-static method gives an accurate LF C-V curve provided there is no leakage through the oxide or through the bulk silicon. If leakage is present, the measured capacitance, in general, will be higher than the actual value. Figure 9.12a shows a quasi-static curve at a slow ramp rate of SOmV/s for a slightly leaky MOS capacitor; the inset shows current that leaks through the sample. If the measured capacitance is now converted to the current using Eq. (9.4) and then the leakage current is subtracted from it and converted back into capacitance, we get the actual capacitance as shown in Figure 9.12b. In this case the real oxide capacitance is 2 x 10- lo F, as against 2.69 x 10- lo F measured from the first curve. Thus, care must be taken with the leakage currents while measuring LF C-V curves. High Frequency C-V Measurement. The commonly used frequency for HF C-V plots is 100KHz-1 MHz, although this frequency is not necessarily high enough to exclude the response of the interface states close to the majority carrier band edges and may lead to a measurement error between 420 9 Data Acquisition and Model Parameter Measurements 'a I I I I -2.5 0 .o 2.5 5.0 3 a 0.5 0 U " 9.0 GATE VOLTAGE V,CV 1 Fig. 9.12 (a) Experimental quasi-static C-V curve ofan MOS capacitor; the inset shows DC leakage current. (b) C-V curve after subtracting the leakage current the flat band voltage and accumulation. The magnitude of the AC signal applied to the sample is typically 10-20mV, so that nonlinear effects are negligible. The DC ramp voltage sweep may be started at any point, but it is recommended to sweep the voltage from + V, to - V, for p-type substrates (- V, to + V, for n-type substrates) in order to avoid problems with minority carrier buildup in the inversion. If the bias is swept from - Vg to + V,, there is a tendency for the C-V curve to go into partial deep depletion and the resulting capacitance is smaller than the true value. However, if the sweep is from + V, to - V,, the resulting capacitance is above the true value but the deviation in this case is small. The true capacitance can be obtained by setting the bias voltage to some value and then waiting for the device to come to equilibrium before applying the next voltage step [lS]. The high frequency (HF) C-V curve is the most commonly measured C-V curve. It is usually not difficult to obtain a valid HF curve, as long as the 9.2 Gate-Oxide Capacitance Measurement 42 1 sample does not have a large series resistance. A series resistance can exist if the back contact is not ohmic, or there is an oxide or insulating layer on top of the gate material, or the polysilicon gate is inadequately doped. If this series resistance is high, the measured capacitance will be lower than the actual value. As a consequence, an error will be introduced in the parameters to be determined from the HF C-V curve [lS]. The presence of series resistance effects can easily be checked by measuring the MOS capacitance in both the series and parallel mode at a particular bias and freq~ency.~ If a significant diflerence exists between the capacitance measured in series and parallel mode then a series resistance is indicated. The value of this resistance can be obtained by biasing the MOS capacitor in heavy accumulation, and reading the series resistance directly from the LCR meter. Once R, is known the actual capacitance can be calculated; for the details of which the reader is referred to [l, p. 2221. 9.2 Gate-Oxide Capacitance Measurement The gate-oxide capacitance per unit area, Cox, is a very important param- eter, since knowledge of its value is essential for accurate modeling of the MOS transistor. Cox can be determined from Eq. (4.1) if to,, the gate oxide thickness, is known. to, can be determined by several methods. The most prevalent methods used during the manufacturing process are optical methods such as ellipsometery [lS], [19], and electrical methods such as the capacitance-voltage (C-V) method 111, [21]-[24]. 9.2.1 Optical Method-Ellipsometry Ellipsometry is the most commonly used optical method for gate oxide thickness (in fact any film thickness) measurement. It involves irradiating the surface of the film with a collimated beam of polarized,6 monochromatic light and analyzing the difference in the polarization between the incident and reflected beams. The measured difference in the state of polarization, in combination with a physical model of the films covering the surface, permit various properties of the films to be computed. The physical model uses the Fresnel equations that describe the reflection of light from the films substrate structure [19]. Most capacitance meters, including the HP 4572A LCR meter, are capable of measuring the capacitance either in series or parallel mode. A plane electromagnetic wave consists of mutually orthogonal electric and magnetic fields. If the amplitude of these fields is a real constant independent of time, the electro- magnetic wave is said to be linearly or plane polarized. The direction of the polarization, by convention, is the direction of electric field. An elliptically polarized wave corresponds to two linearly polarized waves of unequal amplitudes at right angles to each other. 422 9 Data Acquisition and Model Parameter Measurements rLAsER tTELESCOPE COMPENSATOR TECTOR \SUBSTRATE Fig. 9.13 Schematic diagram of a typical ellipsometer Figure 9.13 shows a schematic diagram of a typical ellipsometer, known as the null ellipsometer configuration.' A known controllable state of polarization is obtained using a helium-neon laser, a polarizer, and a quarter-wave compensator. The elliptically polarized light incident upon the sample surface is converted upon reflection into linearly polarized light and passes through an analyzer to the photodetector. If R, and R, are the complex reflection coefficients for the parallel and perpendicular electric field vectors with respect to the plane of incidence, then their ratio gives the following basic equation of ellipsometry: R 3 = (ejA.tan $) RS (9.5) where A (0" I A I 360") represents the change in the phase difference between the parallel and perpendicular components upon reflection and tan $ (Oo 5 t+b I 90') represents the change in the amplitude ratio upon reflection. Both angles $ and A are complicated functions of the index of refraction and film thickness. However, each point in the ($,A) plane corresponds to a unique pair of film index of refraction and film thickness values. Considerable computation is required to obtain a solution and unambiguous results are obtained only if the range of thickness is known. For a detailed mathematical description of the technique and particulars of the computer program the reader is referred to the literature 1191. 9.2.2 Electrical Method The most commonly used electrical method of determining C,, is by measuring the capacitance of an MOS capacitor in accumulation. In fact, There are other types of ellipsometers, such as rotating analyzer ellipsometer, but most commercial ellipsometers are based on null ellipsometer configuration. 9.2 Gate-Oxide Capacitance Measurement 423 the MOS capacitor as a test structure is routinely used to determine Cox. Recall from the discussion in section 4.3, the capacitance of the MOS capacitor measured in accumulation is the gate oxide capacitance [cf. (Eq. 4.62)]. Typically, the capacitance is measured at - 3 V to - 5 V (for p-type substrate) to insure that the device is in accumulation. Since the measured capacitance in accumulation will be the total gate oxide capacitance Cox, dividing Cox by the gate area A, will give Cox( = Cox/Ag). In principle, either the quasi-static or the HF C-V methods, discussed earlier, could be used. However, the HF C-V method is most commonly used to determine Cox, since it is comparatively easy to measure, although care must be taken with series resistance of the MOS capacitor as discussed in section 9.1.3. Note that the measured C,, includes the parasitic capacitance C, of the measuring system which must be subtracted from the measured value before calculating Cox. However, by using a very large area MOS capacitor, C, can often be ignored. Sometimes the measured HF C-V curve does not saturate even in deep accumulation as shown in Figure 9.14. This often is the case for thin insulators (lox < l0OA). In such cases the measured capacitance using the HF C-V method in strong accumulation may not coincide with actual Cox due to the measured Cox being bias dependent as is evident from Figure 9.14. In such situations the correct Cox (corresponding to actual tax) can be deter- mined using derivatives of C-V curve in accumulation [20], [22]. In a method proposed by McNutt and Sah [20], Cox is determined graphically 60 1 I I I I to, = 70 A 1 Accum. h U a v 0" W 0 2 - 2 2 4 0 W I- < W I I I I -5.0 -3.0 -1.0 1.0 3.0 5 GATE VOLTAGE V,,(V) Fig. 9.14 Typical high-frequency C-V plot of an MOS capacitor (p-substrate) with an oxide thickness of 70 424 9 Data Acquisition and Model Parameter Measurements using the following formulation, which is based on Eq. (4.67), where V,( = kT/q) is the thermal voltage and Ch, is the capacitance of the MOS capacitor in F/cm2. The latter is obtained by dividing the measured capacitance by the gate area A, of the MOS capacitor. To find the derivative in Eq. (9.6), we normally use the following approximation (9.7) although the three and five points weighted average technique can also be used 1251. Here Chfl and Chf2 are HF capacitance values per unit area at gate voltages V,, and 1/92, respectively, in accumulation. It has been recently suggested that Cox can be directly obtained by trans- forming Eq. (9.6) in the following form [24] where The advantage of Eq. (9.8) over (9.6) is that the graphical extrapolation is replaced by a simple calculation. A more sophisticated method, which involves the second derivative of the capacitance and which determines Cox at flat band condition, has also been proposed 1221. It has been shown that using Eq. (4.67) one can arrive at a function F(V,) such that' becomes zero at the flat band voltage 1221. Here CL, and Cif indicate the first and second derivatives, respectively, of the measured HF capacitance Ch, with respect to the gate voltage V,. Remember that Ch, is in F/cm2 and is obtained by dividing the measured HF capacitance C,, (Farads) by the gate area A, of the MOS capacitor. The value of V, that makes F zero could then be used to calculate Cox as follows: 1. Calculate the function F from the measured C-V curve using Eq. (9.9) 2. Determine the gate voltage V, = Vgo at which F( V,,) = 0 * For details of the derivation of Eq. (9.9) the reader is referred to the original paper [22]. 9.2 Gate-Oxide Capacitance Measurement 425 3. Calculate C, at the flat band condition from the following equation (9.10) where the + and - signs are for n- and p-substrate, respectively, and chfo and CLfo are values of chf and Ck, respectively, at V, = V,,. 4. Extract C,, using Eq. (4.61) as (9.1 1) This method of determining Cox, and hence to,, has been found to agree within f 2 8, with to, measured using Transmission Electron Microscopy (TEM) 1221. Note that the voltage V,, at which the function F goes to zero is the flat band voltage Vfb, provided the substrate has uniform doping or is almost constant within a Debye length from the Si-SiO, interface. Further, since C, is known at flat band from step 3 above, from Eq. (4.68) for C, and Eq. (4.50) for L,, we can calculate the substrate concentration Nb. The only disadvantage of this method of determining Cox is that we need to calculate first and second derivatives of Chf. It is well known that numerical differentiation in general is less accurate than the parent data. The voltage step used in the C-V measurement is therefore very important. In order to improve results, very small bias steps (from 10 to 50 mV) are normally used near V,, and the capacitance is also calculated as the average of several values (up to 20) measured at the same voltage. This averaging technique is important to reduce the noise in C-V data. The remaining noise in the data is further eliminated by using numerical methods, such as the one proposed by Savitsky and Golay [25]. Their algorithm does not distinguish between smoothing and differentiation, both being handled by a weighted moving average. The weights are selected to give either a smoothing or a derivative of any desired order. The weights are determined by performing a least squares procedure on an assumed cubic, quintic or sexie. The method has proven to be very successful and simple to implement. Gate Oxide Capacitance Measurement Using MOSFET. The MOS capacitor method can easily be extended to measure Cox using a large MOSFET. The experimental setup is shown in Figure 9.15a. The shorted source and drain are connected to the substrate. The gate of the MOSFET is connected to the ‘Hi’ terminal (H,,H,) of the HP4275A LCR meter, whose ‘Lo’ terminal (Lp,Lc) is connected to the substrate. A small AC voltage (20- 30mV peak-to-peak) of frequency 100 KHz is superimposed on the gate voltage which is ramped from - V,(max) (accumulation) to + V,(max) (inversion) and the corresponding gate-to-substrate capacitance C,, measured. [...]... capacitance is c,, = Cox L W + c, (9 .12) where W and L are the effective width and length, respectively, of the MOSFET Figure 9.15b shows measured high frequency gate-to-substrate capacitance C,, as a function of gate voltage V, for a nMOST with W/L = 50/50 and to, = 150w Knowing W and L, one can easily calculate Cox (and hence tax) from Eq (9 .12) It is important to note that for C,, measurement, the parasitic... a given V, is caused by the formation of an inversion channel under the 436 9 Data Acquisition and Model Parameter Measurements 8 I E u 0 7 I I - MOSFET C-V METHOD h 0 z I 6 MOS CAPACITOR C-V MOSFET Vm - V bs METHOD I X v z i 0 I- a LT 4 I- Z w 0 Z g 4 a 2 B 0 3 DISTANCE INTO SILICON, X d ( ~ITI) Fig 9.19 The MOSFET channel doping profile determination using (i) the C-V method (continuous line)... Combining Eqs (2.15) and (4.74) and solving for the substrate concentration N yields (9.13) where A, is the MOS capacitor gate area This is a transcendental equation for N and therefore must be solved iteratively To start the iterations, use a low level of doping, say 1013cm-3, enter into the right hand side and calculate N Next reenter the new value of N into the right hand side and recalculate N ... The I d s - Vgh curve with ps calculated using (a) Eq (9.42)-dotted (b) Eq (9.43)-continuous line Circles are experimental data points line and defined as [cf Eq (6.148)] 1 (9.44) + iQi) g e f f == -( Qb EOEsi where [ = 0.5 for electrons (nMOST), 0.3 for holes (pMOST), and Qb and Qi are bulk and inversion charge densities, respectively The value of 5 is curves are independent of V,, [54] For a such... using the C-V method (a) experimental setup using LCR meter, and (b) gate-to-substrate capacitance CGBoas a function of gate voltage Vg at Vd= 5 V measured using set up shown in (a); nMOST W/L = 50150, to, = 150 A + V,(max) (inversion) and the corresponding gate-to-substrate capacitance C,, measured Figure 9.18b shows CGBo a function of Vgfor an nMOST as with WIL = 50/50 and to, = 150A for a drain/source... dominated by rounding and random errors On the other hand, if the 9.3 Measurement of Doping Profile in Silicon 1501 I (-) 43 1 I I I I GATE VOLTAGE, Vg (V) (+) Fig 9.16 Measurement of doping profile of a double boron implanted MOS capacitor; deep depletion high frequency C-V curve (continuous line) (ii) quasi-static C-V curve (dotted line) (1) 10 - I I I - Eq (9.18) cl E I Eq (9.23) 8- (D b Fig 9.17 Doping... together and reverse biased relative to the substrate via the VA (voltage A) terminal of the HP4140B picoAmmeter A small AC voltage (2 0-3 0mV peak-to-peak) of frequency 1MHz is superimposed on the gate voltage, which is stepped from - V,(max) (accumulation) to 9.3 Measurement of Doping Profile in Silicon 435 EXPANDED -7 .5 -5 .0 -2 .5 0.0 2.5 5.0 75 GATE VOLTAGE Vg ( V ) (b) Fig 9.18 Measurement of MOSFET. .. type of the doping (n- or p-type), the doping concentration will be designated by N only, without subscript Uniform Doping Concentration For an MOS capacitor with uniformly doped substrate, the doping concentration can easily be computed by measuring the minimum and maximum capacitance Cminand C,,,, respectively, of the HF C-V curve This, so called the Cmin C,,, method, is widely used - 9.3 Measurement... expression (9.23) and x,/Ld = ,/5Ld(g - In g - (9.24) 1)lj2 where L, is the Debye length [cf Eq 4.503 The doping concentration factor g2 is defined as (9.25) It is convenient to define a function g1 as (9.26) This function is calculated directly from the measured data and is related to g as 1-9 g-lng-1 _ _ 29_ 1-9 g1 =o (9.27) The variable g2 represents the ratio between the doping calculated with and without... extracted from MOSFET threshold voltage measurements as a function of substrate bias 141 1-[ 47] It is a DC technique requiring only drain current-gate voltage measurements at low V,,( . -I - I 112 HP4140B ; I :DEVICE : I ' UNDER : 1/2 HP4140B : I IcHucKI TEST I L - - - - - - - - -1 I 0 I I -4 Y ox Cr == i -& apos; 0 I- 1- Fig. 9.11. 0" W 0 2 - 2 2 4 0 W I- < W I I I I -5 .0 -3 .0 -1 .0 1.0 3.0 5 GATE VOLTAGE V,,(V) Fig. 9.14 Typical high-frequency C-V plot of an MOS capacitor (p-substrate) with an. [22]. 9.2 Gate-Oxide Capacitance Measurement 425 3. Calculate C, at the flat band condition from the following equation (9.10) where the + and - signs are for n- and p-substrate, respectively,