CONTROLLABILITY/OBSERVABILITY ANALYSIS 397 function will be difficult to control. In a similar vein, the observability of a node depends on the elements through which its signals must propagate to reach an out- put. Its observability can be no better than the observability of the elements through which it must be driven. Therefore, before applying the SCOAP algorithm to a cir- cuit, it is necessary to have, for each primitive that appears in a circuit, equations expressing the 0- and 1-controllability of its output in terms of the controllability of its inputs, and it is necessary to have equations that express the observability of each input in terms of both the observability of that element and the controllability of some or all of its other inputs. Consider the three-input AND gate. To get a 1 on the output, all three inputs must be set to 1. Hence, controllability of the output to a 1 state is a function of the con- trollability of all three inputs. To produce a 0 on the output requires only that a sin- gle input be at 0; thus there are three choices and, if there exists some quantitative measure indicating the relative ease or difficulty of controlling each of these three inputs, then it is reasonable to select the input that is easiest to control in order to establish a 0 on the output. Therefore, the combinational 1- and 0-controllabilities, CC 1 ( Y ) and CC 0 ( Y ), of a three-input AND gate with inputs X 1 , X 2 and X 3 and output Y can be defined as CC 1 ( Y ) = CC 1 ( X 1 ) + CC 1 (X 2 ) + CC 1 (X 3 ) + 1 CC 0 (Y) = Min{CC 0 (X 1 ), CC 0 (X 2 ), CC 0 (X 3 )} + 1 Controllability to 1 is additive over all inputs and to 0 it is the minimum over all inputs. In either case the result is incremented by 1 so that, for intermediate nodes, the number reflects, at least in part, distance (measured in numbers of gates) to pri- mary inputs and outputs. The controllability equations for any combinational func- tion can be determined from either its truth table or its cover. If two or more inputs must be controlled to 0 or 1 values in order to produce the value e, e ∈ {0,1}, then the controllabilities of these inputs are summed and the result is incremented by 1. If more than one input combination produces the value e, then the controllability num- ber is the minimum over all such combinations. Example For the two-input exclusive-OR the truth table is The combinational controllability equations are CC 0 (Y) = Min{CC 0 (X 1 ) + CC 0 (X 2 ), CC 1 (X 1 ) + CC 1 (X 2 )} + 1 CC 1 (Y) = Min{CC 0 (X 1 ) + CC 1 (X 2 ), CC 1 (X 1 ) + CC 0 (X 2 )} + 1  X 1 X 2 Y 000 011 101 110 398 DESIGN-FOR-TESTABILITY The sequential 0- and 1-controllabilities for combinational circuits, denoted SC 0 and SC 1 , are computed using similar equations. Example For the two-input Exclusive-OR, the sequential controllabilities are: SC 0 (Y) = Min{SC 0 (X 1 ) + SC 0 (X 2 ), SC 1 (X 1 ) + SC 1 (X 2 )} SC 1 (Y) = Min{SC 0 (X 1 ) + SC 1 (X 2 ), SC 1 (X 1 ) + SC 0 (X 2 )}  When computing sequential controllabilities through combinational logic, the value is not incremented. The intent of a sequential controllability number is to provide an estimate of the number of time frames needed to provide a 0 or 1 at a given node. Propagation through combinational logic does not affect the number of time frames. When deriving equations for sequential circuits, both combinational and sequen- tial controllabilities are computed, but the roles are reversed. The sequential control- lability is incremented by 1, but an increment is not included in the combinational controllability equation. The creation of equations for a sequential circuit will be illustrated by means of an example. Example Consider a positive edge triggered flip-flop with an active low reset but without a set capability. Then, 0-controllability is computed with CC 0 (Q) = Min{CC 0 (R), CC 1 (R) + CC 0 (D) + CC 0 (C) + CC 1 (C)} SC 0 (Q) = Min{SC 0 (R), SC 1 (R) + SC 0 (D) + SC 0 (C) + SC 1 (C)} + 1 and 1-controllability is computed with CC 1 (Q) = CC 1 (R) + CC 1 (D) + CC 0 (C) + CC 1 (C) SC 1 (Q) = SC 1 (R) + SC 1 (D) + SC 0 (C) + SC 1 (C) + 1  The first two equations state that a 0 can be obtained on the output of the delay flip- flop in either of two ways. It can be obtained either by setting the reset line to 0, or it can be obtained by setting the reset line to 1, setting the data line to 0, and then cre- ating a rising edge on the clock line. Since four events must occur in the second choice, the controllability figure is the sum of the controllabilities of the four events. The sequential equation is incremented by 1 to reflect the fact that an additional time image is required to propagate a signal through the flip-flop. (This is not strictly true since a reset will produce a 0 at the Q output in the same time frame.) A 1 can be achieved only by clocking a 1 through the data line and that also requires holding the reset line at a 1. The Observability Equations The observability of a node is a function of both the observability and the controllability of other nodes. This can be seen in Figure 8.8. In order to observe the value at node P, it must be possible to observe the CONTROLLABILITY/OBSERVABILITY ANALYSIS 399 Figure 8.8 Node observability. value on node N. If the value on node N cannot be observed at the output of the circuit and if node P has no other fanout, then clearly node P cannot be observed. However, to observe node P it is also necessary to place nodes Q and R into the 1 state. There- fore, a measure of the difficulty of observing node P can be computed with the fol- lowing equation: CO(P) = CO(N) + CC 1 (Q) + CC 1 (R) + 1 In general, the combinational observability of the output of a logic gate that drives the input of an AND gate is equal to the observability of that AND gate input, which in turn is equal to the sum of the observability of the AND gate output plus the 1- controllabilities of its other inputs, incremented by 1. For a more general primitive combinational function, the observability of a given input can be computed from its propagation D-cubes (see Section 4.3.3). The pro- cess is as follows: 1. Select those D-cubes that have a D or D only on the input in question and 0, 1, or X on all the other inputs. 2. For each cube, add the 0- and 1-controllabilities corresponding to each input that has a 0 or 1 assigned. 3. Select the minimum controllability number computed over all the D-cubes chosen and add to it the observability of the output. Example Given an AND-OR-Invert described by the equation F = (A · B + C · D), the propagation D-cubes for input A are (D, 1, 0, X) and (D, 1, X, 0). The combina- tional observability for input A is equal to CO(A) = Min{CO(Z) + CC 1 (B) + CC 0 (C),CO(Z) + CC 1 (B) + CC 0 (D)} + 1  The sequential observability equations, like the sequential controllability equa- tions, are not incremented by 1 when computed through a combinational circuit. In general, the sequential controllability/observability equations are incremented by 1 when computed through a sequential circuit, but the corresponding combinational equations are not incremented. P Q R N 400 DESIGN-FOR-TESTABILITY Example Observability equations will be developed for the Reset and Clock lines of the delay flip-flop considered earlier. First consider the Reset line. Its observability can be computed using the following equations: CO(R) = CO(Q) + CC 1 (Q) + CC 0 (R) SO(R) = SO(Q) + SC 1 (Q) + SC 0 (R) + 1 Observability equations for the clock are as follows: CO(C) = Min{CO(Q) + CC 1 (Q) + CC 1 (R) + CC 0 (D) + CC 0 (C) + CC 1 (C), CO(Q) + CC 0 (Q) + CC 1 (R) + CC 1 (D) + CC 0 (C) + CC 1 (C)} SO(C) = Min{SO(Q) + CC 1 (Q) + SC 1 (R) + SC 0 (D) + SC 0 (C) + SC 1 (C), SO(Q) + SC 0 (Q) + SC 1 (R) + SC 1 (D) + SC 0 (C) + SC 1 (C)} + 1  Equations for the Reset line of the flip-flop assert that observability is equal to the sum of the observability of the Q output, plus the controllability of the flip-flop to a 1, plus the controllability of the Reset line to a 0. Expressed another way, the ability to observe a value on the Reset line depends on the ability to observe the output of the flip-flop, plus the ability to drive the flip-flop into the 1 state and then reset it. Observability of the clock line is described similarly. The Algorithm Since the equations for the observability of an input to a logic gate or function depend on the controllabilities of the other inputs, it is necessary to first compute the controllabilities. The first step is to assign initial values to all pri- mary inputs, I, and internal nodes, N: CC 0 (I)= CC 1 (I)= 1 CC 0 (N)= CC 1 (N)= ∞ SC 0 (I)= SC 1 (I)= 1 SC 0 (N)= SC 1 (N)= ∞ Having established initial values, each internal node can be selected in turn and the controllability numbers computed for that node, working from primary inputs to pri- mary outputs, and using the controllability equations developed for the primitives. The process is repeated until, finally, the calculations stabilize. Node values must eventually converge since controllability numbers are monotonically nonincreasing integers. Example The controllability numbers will be computed for the circuit of Figure 8.9. The first step is to initially assign a controllability of 1 to all inputs and ∞ CONTROLLABILITY/OBSERVABILITY ANALYSIS 401 Figure 8.9 Controllability computations. to all internal nodes. After the first iteration the 0- and 1-controllabilities of the inter- nal nodes, in tabular form, are as follows: After a second iteration the combinational 1-controllability of node 7 goes to a 4 and the sequential controllability goes to 0. If the nodes had been rank-ordered—that is, numbered according to the rule that no node is numbered until all its inputs are num- bered—the second iteration would have been unnecessary.  With the controllability numbers established, it is now possible to compute the observability numbers. The first step is to initialize all of the primary outputs, Y, and internal nodes, N, with CO(Y)= 0 SO(Y) = 0 CO(N)= ∞ SO(N)= ∞ Then select each node in turn and compute the observability of that node. Continue until the numbers converge to stable values. As with the controllability numbers, observability numbers must eventually converge. They will usually converge much more quickly, with the fewest number of iterations, if nodes closest to the outputs are selected first and those closest to the inputs are selected last. NCC 0 (N) CC 1 (N) SC 0 (N) SC 1 (N) 62 3 0 0 72 ∞ 0 ∞ 82 3 0 0 92 2 0 0 10 7 4 0 0 R 1 2 3 4 5 6 7 8 9 10 402 DESIGN-FOR-TESTABILITY Example The observability numbers will now be computed for the circuit of Figure 8.9. After the first iteration the following table is obtained: On the second iteration the combinational and sequential observabilities of node 9 settle at 7 and 0, respectively.  SCOAP can be generalized using the D-algorithm notation (cf. Section 4.3.1). This will be illustrated using the truth table for the arbitrary function defined in Figure 8.10. In practice, this might be a frequently used primitive in a library of macrocells. The first step is to define the sets P 1 and P 0 . Then create the intersection P 1 ∩ P 0 and use the resulting intersections, along with the truth table, to create con- trollability and observability equations. The sets P 1 and P 0 are as follows: P 1 = {(0,0,0), (0,1,0), (1,0,1), (1,1,0)} = {(0,x,0), (1,0,1), (x,1,0)} P 0 = {(0,0,1), (0,1,1), (1,0,0), (1,1,1)} = {(0,x,1), (1,0,0), (x,1,1)} The intersection table P 1 ∩ P 0 is as follows: N CO(N) SO(N) 9 ∞∞ 85 0 75 0 65 0 57 0 47 0 38 0 27 0 17 0 ABCZ 00DD D 00D 01DD D01 D 10DD 1D 1D 1D0D 11DD 1 x D D x 1DD CONTROLLABILITY/OBSERVABILITY ANALYSIS 403 Figure 8.10 Truth table for arbitrary function. Note first that some members of P 1 and P 0 were left out of the intersection table. The rows that were omitted were those that had either two or three D and/or D signals as inputs. This follows from the fact that SCOAP does not compute observability through multiple inputs to a function. Note also that three rows were crossed out and two additional rows were added at the bottom of the intersection table. The first of these added rows resulted from the intersection of rows 1 and 3. In words, it states that if input A is a 1, then the value at input C is observable at Z regardless of the value on input B. The second added row results from the intersection of rows 3 and 8. The following controllability and observability equations for this function are derived from P 0 , P 1 , and their intersection: CO(A) = min{CC 0 (B) + CC 0 (C), CC 0 (B) + CC 1 (C)} + CO(Z) + 1 CO(B) = min{CC 1 (A) + CC 1 (C), CC 1 (A) + CC 0 (C)} + CO(Z) + 1 CO(A) = min{CC 0 (A), CC 1 (A) + CC 0 (B),CC 1 (B)} + CO(Z) + 1 CC 0 (Z) = min{CC 0 (A) + CC 1 (C), CC 1 (A) + CC 0 (B) + CC 0 (C),CC 1 (B) + CC 1 (C)} + 1 CC 1 (Z) = min{CC 0 (A) + CC 0 (C), CC 1 (A) + CC 0 (B) + CC 1 (C),CC 1 (B) + CC 0 (C)} + 1 8.3.2 Other Testability Measures Other algorithms exist, similar to SCOAP, which place different emphasis on cir- cuit parameters. COP (controllability and observability program) computes con- trollability numbers based on the number of inputs that must be controlled in order to establish a value at a node. 3 The numbers therefore do not reflect the number of levels of logic between the node being processed and the primary inputs. The SCOAP numbers, which encompass both the number of levels of logic and the number of primary inputs affecting the C/O numbers for a node, are likely to give a more accurate estimate of the amount of work that an ATPG must perform. How- ever, the number of primary inputs affecting C/O numbers perhaps reflects more 0 0 0 0 1 1 1 1 A 0 0 1 1 0 1 0 1 C 1 1 0 0 0 1 1 0 ZB 0 0 1 1 0 0 1 1 404 DESIGN-FOR-TESTABILITY accurately the probability that a node will be switched to some value randomly; hence it may be that it more closely correlates with the probability of random fault coverage when simulating test vectors. Testability analysis has been extended to functional level primitives. FUNTAP (functional testability analysis program) 4 takes advantage of structures such as n- wide data paths. Whereas the single net may have binary values 0 and 1, and these values can have different C/O numbers, the n-wide data path made up of binary sig- nals may have a value ranging from 0 to 2 n – 1. In FUNTAP no significance is attached to these values; it is assumed that the data path can be set to any value i, 0 ≤ i ≤ 2 n − 1, with equal ease or difficulty. Therefore, a single controllability number and a single observability number are assigned to all nets in a data path, independent of the logic values assigned to individual nets that make up the data path. The ITTAP program 5 computes controllability and observability numbers, but, in addition, it computes parameters TL0, TL1, and TLOBS, which measure the length of the sequence needed in sequential logic to set a net to 0 or 1 or to observe the value on that node. For example, if a delay flip-flop has a reset that can be used to reset the flip-flop to 0, but can only get a 1 by clocking it in from the Data input, then TL0 = 1 and TL1 = 2. A more significant feature of ITTAP is its selective trace capability. This feature is based on two observations. First, controllabilities must be computed before observabilities, and second, if the numbers were once computed, and if a change is made to enhance testability, numbers need only be recomputed for those nodes where the numbers can change. The selection of elements for recomputation is simi- lar to event-driven simulation. If the controllability of a node changes because of the addition of a test point, then elements driven by that element must have their con- trollabilities recomputed. This continues until primary outputs are reached or ele- ments are reached where the controllability numbers at the outputs are unaffected by changing numbers at the inputs. At that point, the observabilities are computed back toward the inputs for those elements with changed controllability numbers on their inputs. The use of selective trace provides a savings in CPU time of 90–98% compared to the time required to recompute all numbers in a given circuit. This makes it ideal for use in an interactive environment. The designer visually inspects either a circuit or a list of nodes at a video display terminal and then assigns a test point and imme- diately views the results. Because of the quick response, the test point can be shifted to other nodes and the numbers recomputed. After several such iterations, the logic designer can settle on the node that provides the greatest improvement in the C/O numbers. The interactive strategy has pedagogical value. Placing a test point at a node with the worst C/O numbers is not always the best solution. It may be more effective to place a test point at a node that controls the node in question, since this may improve controllability of several nodes. Also, since observability is a function of controlla- bility, greatest improvements in testability may sometimes be had by assigning a test point as an input to a gate rather than as an output, even though the analysis program indicates that the observability is poor. The engineer who uses the interactive tool, CONTROLLABILITY/OBSERVABILITY ANALYSIS 405 particularly recent graduates who may not have given much thought to testability issues, may learn with such an interactive tool how best to design for testability. 8.3.3 Test Measure Effectiveness Studies have been conducted to determine the effectiveness of testability analysis. Consider the circuit defined by the equation F = A·(B + C + D) An implementation can be realized by a two-input AND gate and a three-input OR gate. With four inputs, there are 16 possible combinations on the inputs. An SA1 fault on input A to the AND gate has a 7/16 probability of detection, whereas an SA0 on any input to the OR gate has a 1/16 probability of detection. Hence a randomly gener- ated 4-bit vector applied to the inputs of the circuit is seven times as likely to detect the fault on the AND gate input as it is to detect a fault on a particular OR gate input. Suppose controllability of a fault is defined as the fraction of input vectors that set a faulty net to a value opposite its stuck-at value, and observability is defined as the fraction of input vectors that propagate the fault effect to an output. 6 Testability is then defined as the fraction of input vectors that test the fault. Obviously, to test a fault, it is necessary to both control and observe the fault effect; hence testability for a given fault can be viewed as the number of vectors in the intersection of the controllability and observability sets, divided by the total number of vectors. But, there may be two reason- ably large sets whose intersection is empty. A simple example is shown in Figure 8.11. The controllability for the bottom input of gate numbered 1 is 1/2. The observability is 1/4. Yet, the SA1 on the input cannot be detected because it is redundant. In another investigation of testability measures, the authors attempt to determine a relationship between testability figures and detectability of a fault. 7 They parti- tioned faults into classes based on testability estimates for the faults and then plotted curves of fault coverage versus vector number for each of these classes. The curves were reasonably well behaved, the fault coverage curves rising more slowly, in gen- eral, for the more difficult to test fault classes, although occasionally a curve for some particular class would rise more rapidly than the curve for a supposedly easier to test class of faults. They concluded that testability data were a poor predictor of fault detection for individual faults but that general information at the circuit level was available and useful. Furthermore, if some percentage, say 70%, of a class of difficult to test faults are tested, then any fixes made to the circuit for testability pur- poses have only a 30% chance of being effective. Figure 8.11 An undetectable fault. 1 3 B A 2 406 DESIGN-FOR-TESTABILITY 8.3.4 Using the Test Pattern Generator If test vectors for a circuit are to be generated by an ATPG, then the most direct way in which to determine its testability is to simply run the ATPG on the circuit. The ability (or inability) of an ATPG to generate tests for all or part of a design is the best criterion for testability. Furthermore, it is a good practice to run test pattern genera- tion on a design before the circuit has been fabricated. After a board or IC has been fabricated, the cost of incorporating changes to improve testability increases dramatically. A technique employed by at least one commercial ATPG employs a preprocess mode in which it attempts to set latches and flip-flops to both the 0 and 1 state before attempting to create tests for specific faults in a circuit. 8 The objective is to find trou- blesome circuits before going into test pattern generation mode. The ATPG compiles a list of those flip-flops for which it could not establish the 0 and/or 1 state. When- ever possible, it indicates the reason for the failure to establish desired value(s). The failure may result from such things as races in which relative timing of the signals is too close to call with confidence, or it could be caused by bus conflicts resulting from inability to set one or more tri-state control lines to a desired value. It could also be the case that controllability to 0 or 1 of a flip-flop depends on the value of another flip-flop that could not be controlled to a critical value. It also has criteria for deter- mining whether the establishment of a 0 or 1 state took an excessive amount of time. Analysis of information in the preprocess mode may reveal clusters of nodes that are all affected by a single uncontrollable node. It is also important to bear in mind that nodes which require a great deal of time to initialize can be as detrimental to testability as nodes that cannot be initialized. An ATPG may set arbitrary limits on the amount of time to be expended in trying to set up a test for a particular fault. When that threshold is exceeded, the ATPG will give up on the fault even though a test may exist. C/O numbers can be used by the ATPG to influence the decision-making process. On average, this can significantly reduce the amount of time required to create test patterns. The C/O numbers can be attached to the nodes in the circuit model, or the numbers can be used to rearrange the connectivity tables used by the ATPG, so that the ATPG always tries to propagate or justify the easiest to control or observe signals first. Initially, when a circuit model is read into the ATPG, connectivity tables are constructed reflecting the interconnections between the various elements in the cir- cuit. A FROM table lists the inputs to an element, and a TO table lists the elements driven by a particular element. By reading observability information, the ATPG can sort the elements in the TO table so that the most observable path is selected first when propagating elements. Likewise, when justifying logic values, controllability information can be used to select the most controllable input to the gate. For example, when processing an AND gate, if it is necessary to justify a 0 on the output of the AND gate, then the input with the lowest 0-controllability should be tried first. If it cannot be justified, then attempt the other inputs, always selecting as the next choice the input, not yet attempted, that is judged to be most controllable. [...]... Analog circuitry represents another problem for scan Memory and analog circuits must be isolated from the digital logic, circuit partitioning becomes critical, and testing strategies for memories and random logic must now coexist Sometimes full-scan is not an option because there is not enough room on the die and the inclusion of additional logic necessitates migrating to a larger die size This could... presence of shadow logic between scan registers and memory.19 This is combinational logic that can not be directly accessed by the scan circuits If the shadow logic consists solely of addressing logic, then it is testable by BIST However, if other random logic is present, it may be necessary to take steps to improve controllability and observability Observability of signals at the address and data inputs... such as asynchronous set and clear inputs and flip-flops whose clock, set, and/ or clear inputs are driven by combinational logic Two problems result when flip-flops are clocked by derived clocks—that is, clocks generated from subcircuits whose inputs are other clocks and random logic signals The first of these problems is that an ATPG may have difficulty creating the clocking signal and keeping it in proper... circuit This approach uses X and Y address lines, as illustrated in Figure 8. 17 Each latch has an X and Y address, as well as clear and preset inputs, in addition to the usual clock and data lines A scan address goes to X and Y decoders for the purpose of generating the X and Y signals that select a latch to be loaded A latch is forced to a 1 (0) by setting the address lines and then pulsing the Preset... 196311 and again in April 1964.12 Detailed description of a scan path and its proposed use for testability and operational modes is described in a patent filed in 1968.13 Discussion of scan path and derivation of a formal cost model were published in 1 973 .14 The level-sensitive scan design (LSSD) methodology was introduced in a series of papers presented at the Design Automation Conference in 1 977 .15 – 17. .. and when testing a circuit It may be the case that a block of logic for example, an ALU or some other deep data path circuit—requires a large number of vectors, but the number of scan-flops used to test the block is quite small On the other hand, there may be a large number of scan-flops involved in control logic The control logic may be quite shallow, perhaps containing only two or three levels of logic. .. methodology Some designs are constrained by area and/ or performance requirements, and some circuitry is not testable by scan Memory blocks, including cache memory, scratchpad memory, fifos, and register banks, which in earlier days were contained in stand-alone chips, now share a common die with logic These memories are normally excluded from the scan chain and tested using memory BIST, as pointed out in... technique used with other scan paths One interesting variant when testing is the fact that the scan path itself can be checked with what is called a flush test.16 In a flush test the A and B clocks are both set high This creates a direct combinational path from the scan-in to the scan-out It is then possible to apply a logic 1 and 0 to the scan-in and observe them directly at the scan output without further... least possible impact on circuit performance and area overhead Slave Jam latch Master Dclk Dclk D Q SI SO_L Sclk Sclk Scan slave Figure 8.16 Flip-flop with dual clock THE SCAN PATH 411 Dclk is used in operational mode, and Sclk is the scan clock Operational data and scan data are multiplexed using Dclk and Sclk When operating in scan mode, Dclk is held high and Sclk goes low to permit scan data to pass... tedious because of all the details that must be maintained while propagating and justifying logic assignments through the time and logic dimensions The task becomes orders of magnitude more difficult when the state machine is implemented using one-hot encoding In that design style, every state is represented by a unique flip-flop, and the circuit becomes an incompletely specified state machine (ISSM)—that . the combinational 1- and 0-controllabilities, CC 1 ( Y ) and CC 0 ( Y ), of a three-input AND gate with inputs X 1 , X 2 and X 3 and output Y can. (x,1,1)} The intersection table P 1 ∩ P 0 is as follows: N CO(N) SO(N) 9 ∞∞ 85 0 75 0 65 0 57 0 47 0 38 0 27 0 17 0 ABCZ 00DD D 00D 01DD D01 D 10DD 1D 1D 1D0D 11DD 1 x D D x 1DD CONTROLLABILITY/OBSERVABILITY. access and control of sequential storage elements in a circuit. This approach uses X and Y address lines, as illustrated in Figure 8. 17. Each latch has an X and Y address, as well as clear and preset