1 NATIONAL UNIVERSITY OF HO CHI MINH CITY UNIVERSITY OF INFORMATION TECHNOLOGY FACULTY OF COMPUTER ENGINEERING LECTURE Lecturer: Lam Duc Khai VERILOG Hardware Design Language Chapter9: Testbench and Verification Subject: 2 Agenda 1. Chapter 1: Introduction ( Week1) 2. Chapter 2: Fundamental concepts (Week1) 3. Chapter 3: Modules and hierarchical structure (Week2) 4. Chapter 4: Primitive Gates – Switches – User defined primitives (Week2) 5. Chapter 5: Structural model (Week3) 6. Chapter 6: Behavioral model – Combination circuit & Sequential circuit (Week4 & Week5) 7. Chapter 7: Tasks and Functions (Week6) 8. Chapter 8: State machines (Week6) 9. Chaper 9: Testbench and verification (Week7) 3 Agenda 4  Pre-synthesis verification: Design Specification Behavior Description Pre-synthesis verification Compilation and Synthesis Timing analyis Post-synthesis verification Routing and Placement Physical layout Chip + Check design function flaws that may cause by ambiguous problem specification, designer errors, or incorrect use of parts in the design. + Done by simulation (presynthesis simulation), assertion verification with testbench definition or input waveform. CAD flow reminder 5  Function verification with input waveform: Define input waveform manually CAD flow reminder (Cont’d) 6  Function verification with testbench: • A testbench is used to verify that the logic is correct. The testbench instantiates the logic under test. It reads a file of inputs and expected outputs called test -vectors, applies them to the module under test, and logs mismatches. • Testbench is a code for test, not a part of final design. CAD flow reminder (Cont’d) 7  Function verification with testbench: CAD flow reminder (Cont’d) 8 Structure of a testbench •Structure1 9 Structure of a testbench (Cont’d) •Structure1 (Cont’d) 10 Structure of a testbench (Cont’d) •Structure1 (Cont’d) [...]...Structure of a testbench (Cont’d) •Structure1 (Cont’d) 11 Structure of a testbench (Cont’d) •Structure2 module testbench; parameter declaration declaration such as the signal (reg [7:0] dat, … and so on) This part is same to Verilog RTL programming in the previous pages design module instances always sentence initial sentence Used for generating clock signals and other signals definition... definition of function definition of task endmodule Used to give initial value to the signals and to create signals in time sequence 12 Structure of a testbench (Cont’d) •Structure2 (Cont’d) D_FF example: module dff (d ,clk, q ); input d, clk; output q; reg q; always @(posedge clk) q . Hardware Design Language Chapter9: Testbench and Verification Subject: 2 Agenda 1. Chapter 1: Introduction ( Week1) 2. Chapter 2: Fundamental concepts (Week1) 3. Chapter 3: Modules and hierarchical structure. & Week5) 7. Chapter 7: Tasks and Functions (Week6) 8. Chapter 8: State machines (Week6) 9. Chaper 9: Testbench and verification (Week7) 3 Agenda 4  Pre-synthesis verification: Design Specification Behavior. (Cont’d) 6  Function verification with testbench: • A testbench is used to verify that the logic is correct. The testbench instantiates the logic under test. It reads a file of inputs and expected