Điện Tử - Cơ Sở Thiết Kế Mạch - Design Trên Máy Tính (Phân 2) part 14 ppsx

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Điện Tử - Cơ Sở Thiết Kế Mạch - Design Trên Máy Tính (Phân 2) part 14 ppsx

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Chung 1<1 eo Ihe bicu di~n alamal MoOiC trcn ng6n ngii' VHDL luong It! nlw khi hicu dien de tll<.Kh co nh6 Iren mue thanh ghi. QU,I Irlnb bteu dicn olomal hli"u 11< 1ll sc duqe chi a thanh hai phflll h¢: pbfm b¢ I(} lHrp V;I phtm h¢ m,.teh IU{11l I~r. Tin hi¢u xoa In.mg II1 li khon,!! dong b(l kh6i lao gia Irj cho dc thanh gbi v;\ tlu'a 61l'Hnal \'e tn.mg thai ban dilu. Om!;! \'6i Sl.f xufil hten sLt"(\n ella tin hi¢u cl6ng b(l CLK. gii.l trj eua tn.mg Ihili m6i duq'c gi.ln eho lfi.mg Lh,li hi¢n thoi Ph:m h¢ mi \eh 10 hqp inO ti.l mach t6 heyp tinh IO<.lrl 1i"i lllg th{li moi \,;1 m,.tch t6 htjp linh loan gia trj d.lu ra. Doi \'('ri otomal ,\1oore, Lin hi¢u d'-Iu ra chi phV Ihw)e \',10 tl"i~ng thLii hi¢n Ihc)"! [len m;.Icb to ]HJP XL\c djnh d.lu ra kh6ng J cl n6i \'oi de tin hi~u \'ao. Dnoi dtlY chung 1<.1 X~I vi dl} X:ly d~rng chu'ong Irlllh tren ngon ngu YI-IDL me) t.i otomat Moon: di(iu khiC::n 111<.lel1 cong bai so nguyen dau rldy tlnb. Vi d~l. X{IY dl,J.'ng m".lCh dieu kllien phcp toan et)l1g hal so nguyen. SCi c!(i Illu.)t loan dll\"fC dlt"a ra trcn hl11h 7.17. Cae so du'Ung dWJc IUtl IfLf du6i d'.lI1g mil Lr~rc ticp con de so [un duc/c Iuu Irtf theo d'.l11g mil bu hai. Thco set do IhLJi.~t tOiln. chung ta Xi.ly dl.rng dutjc so d() chuycn Irang thai ella (l(omat Moon: tLt"cJ'ng Crng (hlnh 7.16). Tr(;n hillll 7.17, de Irt.lI1g (h<.i.i clm (Mllllal Moore ntun tuung ung \'6i uk kh6i thVe hi~n phep Imin \,~l khollg ghi trong d{lu ngo(\c cion. 234 ()Iomat Moore nay co de tin hi¢u vuo ta: X = I x I ' x 2 ' x, I; cae tin hi~u fa I~\: Y = I YI' Y2' y" y~ I: eae tn.ltlg Ihai I~\: S = I SI\' SI ' S2 . S; , S~ , S'i I: , " , , " /', , , ' , , s, ~, " " " S, \, \, .\,\, IIlllh 7,16, So (\6 chllytn (rang lhji [lla (l\clnlal l"Ihlore ttrUllg l~rng \"O'i tliutl1to,in tl"en hln11 7.\7. Ci, Begin (~(,) sign sm 0 X, s, () x: sign Reg y, sign sm o , . , (~\l x, 0 P,P" . ./ PIP;> S, , . , h"j end IIlnh 7.17. So d6 [huilt to;ln (Illre hi0n pilcp COil}:': hai ~O c(\ (![I'll ph:iy lillh. Do' Ill ciuro'ng tflnh dlffJ'i day m6 I,', 11191 ph[in ella olonla! Moore 1161 trC:ll. entity MoorcSum is port ( elK. RST: in BIT: X: in BIT-VECTOR ( 3 downto 1 i: Y: out BIT-VEe/OR (4 downto Iii: cnd Moon:Sum; 235 236 architecture Implement of MooreSum is begin process ( eLK, RST. x ) hegin type StateType is ( SO, SI, S2, S3, S.\, S5 ) variable State, NextStatc: StateType; ire RST~ 'I') then for I in I to 4 loop YO) <~ '0'; end loop; S <~ SO; c1sif ( CLK'evcnt and eLK:::: ' l' ) then State := NcxtState; end if case State is when SO => for I in 1 to 4 loop Y( I ) <~ '0'; end loop: if ( X( I ) ~ 'I' ) then NcxtState ;:::: 51; clsiF ( X( 2 ) ~ 'I' ) then NcxtState := 53; else NcxtStale := S2; cndiL when 51 => Y( I ) <~ '1'; iF ( X( 2 ) ~ 'I' ) then NexlState := S3; else NCxlState := S2; end if; 2. 1\1i) hlllh ht'Ja blumat Mealy Gtomat Mealy tiS c[le h(lI11 clI.lIY~1l lrang Ih.li vll hil.lll ra dlfOC bieu (hen Iheo h~ thue au: s( I ) = 5( s( I - I ). x( I ) ) y(l) = 1,( s( I ). x( I ) ) 1=1. 2 Doi \'ai 016mal Mealy. c k 1111 hi~u dau fa Iii plly thu(x: vilo ,r.mg Ih.ii \,;1 1111 hi¢u dau vilO a Ihai di~1ll hi¢n Ihal. Nlur v~ly. lin hi¢u d ill ra co Ih~ 11m) doi 1l(:'1I Illl hll:lI d;ill vao bi Ihay deli (fOng Ihai gian Xu;}1 hi~n xung nhjp dong h6. Dieu d6 1;1111 elm lin hi¢u dilu ra ella 616mal Mealy eo Ihe IU l: thui nh(ln gi.i 11"1 ! hong d~t do.in Int&: do c6 Sl.( In: lill hi~u , xcI tlr Ihoi diem 1111 hi¢u \,~IO Ihay (1\-)i den Ihai dllim 111(1 giii 11"1 dau fa ella phan Ilr Dip-flop Ihay dbi. D~ ng~1ll ch(m ~f Ihay doi gi:i If! dilU I"a Irong Ihoi gian Ion 1 •. 1.1 Cl'I.1 xling dong 1>9. clUing la ph ' li dong b¢ h6'l ho< . 1I dQng cua olomal Mealy )"hong dong b(>. Dt! d~ll du~ dieu nay. lin hi¢u di vao hL,' 1ll'.ICh I1l1a I r'.lIlg 11 1 ph.ii dU"qc dong bQ bllllg xung dong h6 \'ll khi do lin hll;u dilu ra phai duqc xiic djnh chi trong Ihai gian Ihi(:1 h}p suan Clll .l. xung d6ng h6. Cung giang !lluf 016mal rvloorc, 610mat r lealy cung duqc mo Iii Irl:1l ngon ng[( VHDL b{lng hai phflll b~: ph;ln h~ m •. lch 10 hqp xuc dinh ham ra \"(li h:1.I11 chuyen Irang Ih;ii \,~I phfm h~ ]11'.ICI1 nhi.1 dong bej. 016mal Mealy co th e; duqc x;iy d~fI1g Iheo hai dang: dang nwch khong dong h9 (I:"ILI ra Vi\ d' .l llg lIlilch dong b¢ <hiu fa. ClUing la hay :xcI dell,! :X I), dl:rng mach dieu khit:!n Ilwc hi~n phcp c(mg hai so dJ"u ph iy linh dJ neu a nWc IrUCK:. Olomill Mealy luang ling vai Ihu(1.l Imin IIl:n hinh 7.17 co gian dO ehuy~n Ir'. lIlg th,ii mo t:1 Irl:11 hll1h 7.18. 016mal Mculy nh (1Il dm: ;1C se co de Ihong so ~au: , " ; . " \. s, )_ ' <" " {s,'\ ' Il,lng th,il CU'L a lom;]] ~1c'Lly IHOLlg lmg H1L Ihu;lllo;iLllfl'Ll hiLlh 7. 17. Cae tin hi¢u ra I~I: Y = I y, . y, . h y, I: Cic In. lIlg th ai lit: S = I 5". S, ' S, . S, I: l\'hu \'(Iy eilting t<l th[iy rtmg. v6i clmg m()t thu(1t to{lIl. Ihit'! ke~ theo m6 hinh !\kaly sc IIC~\ Ktbn tn.lllg thai hOn so vui thici hi theo mo hlnh ~10orc. Nell x.fiy tlvng (Jt(mutt l\:kalv theo thiel kc kh(ll1" Ml11!! • c _ ht). Sti dtJ ella o\(mla\ '-;C ell dang nln!" Iren hlllh 7.19. Tron,g ph{m h0 mach nht)' dt)ng h~l, \'i~e kich hOill Iri.li1g Ihili kh6ng dong b(l (asynehoronous reset) d(tt gi<i Irj dilll cho ole thanh ghi \'il dlr,\ m,iy \'C tr;.\l1g th,.li ban cHill. M6i I;ln XU;')I hien ,'-;LTi)n ella tin hiell eLK giil tr! eua Iqmg thai m6i I ["(). Ihi:lnh tf' Ii1& th,ii hien ti1(1i. Philn h¢ to h9'P eUil o\(')lnal m6 Input {~ Mach 10 hdP Output thanh ghi trang thai} Hinh 7.llJ. So do Il;!u}l:1115' Cll~1 Olomal l\h;,lly \l(Mt tilIng Illl'o ch':~ d6 khong: c161lg hO d:iu ra. Iii 16gie eLla vi¢c t~\O tr~lI1g th,l.i m6i vii tin hl~u (Hill ra ella h~ Ih6n~. l)oan chunng trinh dUoi (%y bieu elien olomal ~1ea\y t!leo Illiel k6 khong d6n~ be) ella t\l\Ii~\ IOil.1l e(l11g hai s6 e6 dfill phuy tinh d.1 neu (j nwe Inroc. cntit.\/ AsyncMcaly is purl ( eLK. RST: in IllT: X: in IllT-YECfOR ( 3 down I" I ): Y: out BIT-VECTOR (4 downto ! ) 1: cnd ASYlle\1ca\y; architecture Implement of' Asynct' kal)! IS hcgin IH"OCl'SS ( elK, RST, x ) hC:,!in typc StaleTypc is ( SO. S1. S2. S1 ): "ariablc Slale, t\extSlak: StatcTypc : ire RST='I')lhrn Slate := SO: clsif ( ClK'cvcnt and CLK::: '1' ) thcn Slate := NextState: end if: case Stall.: is wll{'l1 SO => if ( X( 1 ) ~ 'I' ) then Y( 1 ) ~ 'I': NcxtState := S I: elsif ( X( 2 ) = 'J' ) then Y( 3 ) ~ '1': NcxtStatc := S2: clse Y(2)~'I': NcxlSlalc := S2: end if: when SI => Chung ta Ih,-Y1' r{mg. trung 6t6rnat Mealy kh(lIlg d6ng, h<), q.r if ( X( 2 ) ~ , I' ) then Y(J)~'I': NextState := S1: else Y(2)='I': NextState := S2: end if: Out xu,!'t hicn tin hi¢u d[iu fa khollg In elm"Ck ~ pct 1 >1 ~ (king h0 \'6i tIll !1!~U cUu \'(10. I:)ieu ll~ly co th~ :-;0 dtlll t6i nhullg ket qua thve llicn pll~p tlni1 sai. Dc h.h,k [11lL,JC nhu(.1c diC:rn ella (J\()1lwt Mo.:aly kilong dong b(l. cilLing ta sC: th0m do trong lll<'lCh 11lt)t h¢ nh6 d6ng be). I k nila nay ntull giua mi.Kil 10 lH)"p tfnh 10;111 ham ra \'6i dfiu ra eua btolllat. Thong tl1u'O'ng de phfin tt'r ella ]11'.lel1 I1ha dong h(l nilY la de [111,111 Ill' flip-flop. Cae flip-flop il\IY ~ M<Jcll f-~ to hdp ~ lhanh ghl } > , cloeS llinh 7.20. So (ki nguyenl)' ella atom at !'Ileal)' hoat d(lllg thea ch0 db dong ba rial! [,L 23') dll'CYc dong \-x? theo SUl)']l gi6ng nlur cae thanh ghi tqmg thai. Khi XlUY\ hi~Jl xlIng d61l~ b{\ trong th{\i gian thiel ltlp sU'O'n cua tin hi¢u dong ho. h¢ mi,tell nh6 d[iu ra ilh,~n gi,i Ir! do m' tch Ie} hqp xac J!nh hiun nl tfnh to,-in ducyc. Trong to<'111 b() khO<lng th(ji gian sau khi xung tU'ing h6 thie~t l<~p SHall. h¢ mach nila kh6ng thay doi tn.lI1g thili. Dieu nay lam cbo trong kho:mg thCii giitn t6n t~\i CLl<1 xung dong h6, gi{\ tf! eLla cae tin hi~u d,lu ra kh(mg thay d6i eho clil tin hiGu d:iu \,~10 eo the: b! thay deli do nhD"JIg I}' do khuch qua. Ch(illg 1a ell the 1116 til d.e hi:un ehuycn tn.lI1g thiii trong phtill dOllg b(l ella chuong trltlh VHDL. Doi voi 6t6mal Mealy theo thU;:lt tOLIIl trell hlnh 7.17. thi6t k6 \"()'j 1l1i.leh d6ng b{) driu ra se ctuQe bieu dil:ll btmg ngoll ngu' VJ-1Dl nhu du6i d[\v. 240 entity SYllc\.1ealy is pori ( eLK. RST: in IlIT: X: in IlIT-VECTOR (3 downlo I ): Y: ouIIllT-VECTOR (4 downlo I )): end Sync MeaL Hrchih'cture Implement of SyneMe.:tl is' begin process ( ClK, RST. X ) begin Iype 5tateType is (SO. SI. S2, 53. S): yariable State: StatcType; iF (RST ~ 'I' ) Ihen State := SO; elsif ( CLK'event Hnd CLK ::: 'I' ) then case State is when SO => if ( XI I ) ~ 'I' ) then Y( I ) <~ '1': State := Sl; . ]11'.lel1 I1ha dong h(l nilY la de [111,111 Ill' flip-flop. Cae flip-flop ilIY ~ M<Jcll f-~ to hdp ~ lhanh ghl } > , cloeS llinh 7.20. So (ki nguyenl)'. dil:ll btmg ngoll ngu' VJ-1Dl nhu du6i d[v. 240 entity SYllc.1ealy is pori ( eLK. RST: in IlIT: X: in IlIT-VECTOR (3 downlo I ): Y: ouIIllT-VECTOR (4 downlo I )): end. cntit./ AsyncMcaly is purl ( eLK. RST: in IllT: X: in IllT-YECfOR ( 3 down I" I ): Y: out BIT-VECTOR (4 downto ! ) 1: cnd ASYlle1cay; architecture Implement

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