TPIC6B595 POWER LOGIC 8-BIT SHIFT REGISTER SLIS032 – JULY 1995 1 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Low r DS(on) 5 Ω Typical Avalanche Energy 30 mJ Eight Power DMOS-Transistor Outputs of 150-mA Continuous Current 500-mA Typical Current-Limiting Capability Output Clamp Voltage . . . 50 V Devices Are Cascadable Low Power Consumption description The TPIC6B595 is a monolithic, high-voltage, medium-current power 8-bit shift register designed for use in systems that require relatively high load power. The device contains a built-in voltage clamp on the outputs for inductive transient protection. Power driver applications include relays, solenoids, and other medium- current or high-voltage loads. This device contains an 8-bit serial-in, parallel-out shift register that feeds an 8-bit D-type storage register. Data transfers through both the shift and storage registers on the rising edge of the shift-register clock (SRCK) and the register clock (RCK), respectively. The storage register transfers data to the output buffer when shift- register clear (SRCLR ) is high. When SRCLR is low, the input shift register is cleared. When output enable (G) is held high, all data in the output buffers is held low and all drain outputs are off. When G is held low, data from the storage register is transparent to the output buffers. When data in the output buffers is low, the DMOS-transistor outputs are off. When data is high, the DMOS- transistor outputs have sink-current capability. The serial output (SER OUT) allows for cascading of the data from the shift register to additional devices. Outputs are low-side, open-drain DMOS transistors with output ratings of 50 V and 150-mA continuous sink- current capability. Each output provides a 500-mA typical current limit at T C = 25°C. The current limit decreases as the junction temperature increases for additional device protection. The TPIC6B595 is characterized for operation over the operating case temperature range of –40°C to 125°C. Copyright  1995, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 NC V CC SER IN DRAIN0 DRAIN1 DRAIN2 DRAIN3 SRCLR G GND NC GND SER OUT DRAIN7 DRAIN6 DRAIN5 DRAIN4 SRCK RCK GND DW OR N PACKAGE (TOP VIEW) logic symbol † 2 SRG8 † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. 9 12 8 13 3 EN3 C2 R C1 1D G RCK SRCLR SRCK SER IN 4 6 5 14 7 16 15 18 17 DRAIN0 DRAIN1 DRAIN2 DRAIN3 DRAIN4 DRAIN5 DRAIN6 DRAIN7 SER OUT 2 NC – No internal connection TPIC6B595 POWER LOGIC 8-BIT SHIFT REGISTER SLIS032 – JULY 1995 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 logic diagram (positive logic) G RCK SRCLR SRCK SER IN CLR D C1 D C2 CLR D C1 SER OUT CLR D C1 CLR D C1 CLR D C1 CLR D C1 CLR D C1 CLR D C1 D C2 D C2 D C2 D C2 D C2 D C2 D C2 4 DRAIN0 5 DRAIN1 10, 11, 19 GND 6 DRAIN2 7 DRAIN3 14 DRAIN4 15 DRAIN5 16 DRAIN6 17 DRAIN7 9 8 3 12 13 18 TPIC6B595 POWER LOGIC 8-BIT SHIFT REGISTER SLIS032 – JULY 1995 3 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 schematic of inputs and outputs EQUIVALENT OF EACH INPUT TYPICAL OF ALL DRAIN OUTPUTS V CC Input GND GND DRAIN 50 V 20 V 25 V 12 V absolute maximum ratings over recommended operating case temperature range (unless otherwise noted) † Logic supply voltage, V CC (see Note 1) 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Logic input voltage range, V I –0.3 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power DMOS drain-to-source voltage, V DS (see Note 2) 50 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Continuous source-to-drain diode anode current 500 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pulsed source-to-drain diode anode current (see Note 3) 1 A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pulsed drain current, each output, all outputs on, I D , T C = 25°C (see Note 3) 500 mA. . . . . . . . . . . . . . . . . . . Continuous drain current, each output, all outputs on, I D , T C = 25°C 150 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . Peak drain current single output, I DM ,T C = 25°C (see Note 3) 500 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Single-pulse avalanche energy, E AS (see Figure 4) 30 mJ. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Avalanche current, I AS (see Note 4) 500 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Continuous total dissipation See Dissipation Rating Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating virtual junction temperature range, T J –40°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating case temperature range, T C –40°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Storage temperature range –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltage values are with respect to GND. 2. Each power DMOS source is internally connected to GND. 3. Pulse duration ≤ 100 µs and duty cycle ≤ 2%. 4. DRAIN supply voltage = 15 V, starting junction temperature (T JS ) = 25°C, L = 200 mH, I AS = 0.5 A (see Figure 4). DISSIPATION RATING TABLE PACKAGE T C ≤ 25°C POWER RATING DERATING FACTOR ABOVE T C = 25°C T C = 125°C POWER RATING DW 1389 mW 11.1 mW/°C 278 mW N 1050 mW 10.5 mW/°C 263 mW TPIC6B595 POWER LOGIC 8-BIT SHIFT REGISTER SLIS032 – JULY 1995 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 recommended operating conditions MIN MAX UNIT Logic supply voltage, V CC 4.5 5.5 V High-level input voltage, V IH 0.85 V CC V Low-level input voltage, V IL 0.15 V CC V Pulsed drain output current, T C = 25°C, V CC = 5 V (see Notes 3 and 5) –500 500 mA Setup time, SER IN high before SRCK↑, t su (see Figure 2) 20 ns Hold time, SER IN high after SRCK↑, t h (see Figure 2) 20 ns Pulse duration, t w (see Figure 2) 40 ns Operating case temperature, T C –40 125 °C electrical characteristics, V CC = 5 V, T C = 25°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT V (BR)DSX Drain-to-source breakdown voltage I D = 1 mA 50 V V SD Source-to-drain diode forward voltage I F = 100 mA 0.85 1 V V OH High-level output voltage, I OH = –20 µA, V CC = 4.5 V 4.4 4.49 V V OH gg, SER OUT I OH = –4 mA, V CC = 4.5 V 4 4.2 V V OL Low-level output voltage, I OL = 20 µA, V CC = 4.5 V 0.005 0.1 V V OL g, SER OUT I OL = 4 mA, V CC = 4.5 V 0.3 0.5 V I IH High-level input current V CC = 5.5 V, V I = V CC 1 µA I IL Low-level input current V CC = 5.5 V, V I = 0 –1 µA I CC Logic su pp ly current V CC =55V All outputs off 20 100 µA I CC Logic s u ppl y c u rrent V CC = 5 . 5 V All outputs on 150 300 µ A I CC(FRQ) Logic supply current at frequency f SRCK = 5 MHz,C L = 30 pF, All outputs off, See Figures 2 and 6 0.4 5 mA I N Nominal current V DS(on) = 0.5 V, I N = I D ,T C = 85°C See Notes 5, 6, and 7 90 mA I DSX Off state drain current V DS = 40 V, V CC = 5.5 V 0.1 5 µA I DSX Off - state drain c u rrent V DS = 40 V, V CC = 5.5 V, T C = 125°C 0.15 8 µ A I D = 100 mA, V CC = 4.5 V 4.2 5.7 r DS(on) Static drain-source on-state resistance I D = 100 mA, T C = 125°C, V CC = 4.5 V See Notes 5 and 6 and Figures 7 and 8 6.8 9.5 Ω I D = 350 mA, V CC = 4.5 V 5.5 8 NOTES: 3. Pulse duration ≤ 100 µs and duty cycle ≤ 2%. 5. Technique should limit T J – T C to 10°C maximum. 6. These parameters are measured with voltage-sensing contacts separate from the current-carrying contacts. 7. Nominal current is defined for a consistent comparison between devices from different sources. It is the current that produces a voltage drop of 0.5 V at T C = 85°C. TPIC6B595 POWER LOGIC 8-BIT SHIFT REGISTER SLIS032 – JULY 1995 5 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 switching characteristics, V CC = 5 V, T C = 25°C PARAMETER TEST CONDITIONS MIN TYP MAX UNIT t PLH Propagation delay time, low-to-high-level output from G 150 ns t PHL Propagation delay time, high-to-low-level output from G C L = 30 pF, I D = 100 mA, 90 ns t r Rise time, drain output L , D , See Figures 1, 2, and 9 200 ns t f Fall time, drain output 200 ns t a Reverse-recovery-current rise time I F = 100 mA, di/dt = 20 A/ µ s, 100 ns t rr Reverse-recovery time F , µ , See Notes 5 and 6 and Figure 3 300 ns NOTES: 5. Technique should limit T J – T C to 10°C maximum. 6. These parameters are measured with voltage-sensing contacts separate from the current-carrying contacts. thermal resistance PARAMETER TEST CONDITIONS MIN MAX UNIT R θJA Thermal resistance junction to ambient DW package All 8 out p uts with equal p ower 90 ° C/W R θJA Thermal resistance , j u nction - to - ambient N package All 8 o u tp u ts w ith eq u al po w er 95 °C/W PARAMETER MEASUREMENT INFORMATION TEST CIRCUIT 5 V V CC DRAIN GND SRCLR SER IN R L = 235 Ω C L = 30 pF (see Note B) VOLTAGE WAVEFORMS G Output SRCK RCK Word Generator (see Note A) 76543210 5 V SRCK 5 V G 5 V SER IN RCK SRCLR 5 V 5 V DUT 24 V DRAIN1 24 V 0 V 0 V 0 V 0.5 V 0 V 10, 11, 19 8 13 3 12 9 0 V 4–7, 14–17 I D 2 NOTES: A. The word generator has the following characteristics: t r ≤ 10 ns, t f ≤ 10 ns, t w = 300 ns, pulsed repetition rate (PRR) = 5 kHz, Z O = 50 Ω. B. C L includes probe and jig capacitance. Figure 1. Resistive-Load Test Circuit and Voltage Waveforms TPIC6B595 POWER LOGIC 8-BIT SHIFT REGISTER SLIS032 – JULY 1995 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PARAMETER MEASUREMENT INFORMATION 4–7, 14–17 TEST CIRCUIT SWITCHING TIMES G 5 V 50% 24 V 0.5 V 90% 10% t PLH t r 50% 90% 10% t PHL t f SRCK 5 V 50% SER IN 5 V 50% 50% t su t h t w INPUT SETUP AND HOLD WAVEFORMS 5 V 24 V V CC DRAIN SRCLR SER IN R L = 235 Ω C L = 30 pF (see Note B) G Output SRCK RCK DUT GND Output Word Generator (see Note A) 10, 11, 19 8 13 3 12 9 0 V 0 V 0 V I D 2 NOTES: A. The word generator has the following characteristics: t r ≤ 10 ns, t f ≤ 10 ns, t w = 300 ns, pulsed repetition rate (PRR) = 5 kHz, Z O = 50 Ω. B. C L includes probe and jig capacitance. Figure 2. Test Circuit, Switching Times, and Voltage Waveforms 0.1 A I F 0 I RM 25% of I RM t a t rr di/dt = 20 A/µs + – 2500 µF 250 V L = 1 mH I F (see Note A) R G V GG (see Note B) Driver TP A 50 Ω Circuit Under Test DRAIN 25 V t 1 t 3 t 2 TP K TEST CIRCUIT CURRENT WAVEFORM NOTES: A. The DRAIN terminal under test is connected to the TP K test point. All other terminals are connected together and connected to the TP A test point. B. The V GG amplitude and R G are adjusted for di/dt = 20 A/µs. A V GG double-pulse train is used to set I F = 0.1 A, where t 1 = 10 µs, t 2 = 7 µs, and t 3 = 3 µs. Figure 3. Reverse-Recovery-Current Test Circuit and Waveforms of Source-to-Drain Diode TPIC6B595 POWER LOGIC 8-BIT SHIFT REGISTER SLIS032 – JULY 1995 7 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PARAMETER MEASUREMENT INFORMATION 15 V 10.5 Ω 200 mH SINGLE-PULSE AVALANCHE ENERGY TEST CIRCUIT t w t av I AS = 0.5 A V (BR)DSX = 50 V VOLTAGE AND CURRENT WAVEFORMS Input I D V DS See Note B V CC DRAIN SRCLR SER IN G SRCK RCK Word Generator (see Note A) DUT GND 5 V V DS I D 2 8 13 3 12 9 10, 11, 19 4–7, 14–17 5 V 0 V MIN NOTES: A. The word generator has the following characteristics: t r ≤ 10 ns, t f ≤ 10 ns, Z O = 50 Ω. B. Input pulse duration, t w , is increased until peak current I AS = 0.5 A. Energy test level is defined as E AS = I AS × V (BR)DSX × t av /2 = 30 mJ. Figure 4. Single-Pulse Avalanche Energy Test Circuit and Waveforms TYPICAL CHARACTERISTICS 2 1 10 4 0.1 0.2 10.4 2 104 0.2 0.1 0.4 I – Peak Avalanche Current – A AS PEAK AVALANCHE CURRENT vs TIME DURATION OF AVALANCHE t av – Time Duration of Avalanche – ms T C = 25°C Figure 5 I – Supply Current – mA CC SUPPLY CURRENT vs FREQUENCY f – Frequency – MHz 1 0.5 0 0.1 1 10 1.5 2 100 2.5 V CC = 5 V T C = –40°C to 125°C Figure 6 TPIC6B595 POWER LOGIC 8-BIT SHIFT REGISTER SLIS032 – JULY 1995 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TYPICAL CHARACTERISTICS Figure 7 10 8 4 2 0 6 0 100 200 300 400 14 12 16 DRAIN-TO-SOURCE ON-STATE RESISTANCE vs DRAIN CURRENT 18 500 600 700 I D – Drain Current – mA V CC = 5 V See Note A T C = 25°C T C = –40°C T C = 125°C Ω DS(on) – Drain-to-Source On-State Resistance –r Figure 8 V CC – Logic Supply Voltage – V STATIC DRAIN - TO - SOURCE ON - STATE RESISTANCE vs LOGIC SUPPLY VOLTAGE 4 3 1 0 4 4.5 5 5.5 5 7 8 6 6.5 7 6 2 T C = 125°C T C = 25°C T C = – 40°C I D = 100 mA See Note A Ω DS(on) – Static Drain-to-Source On-State Resistance –r Switching Time – ns SWITCHING TIME vs CASE TEMPERATURE –50 T C – Case Temperature – °C I D = 100 mA See Note A 200 150 100 50 250 300 t PHL t PLH t r t f –25 0 25 50 75 100 125 Figure 9 NOTE C: Technique should limit T J – T C to 10°C maximum. TPIC6B595 POWER LOGIC 8-BIT SHIFT REGISTER SLIS032 – JULY 1995 9 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 THERMAL INFORMATION Figure 10 – Maximum Continuous Drain Current MAXIMUM CONTINUOUS DRAIN CURRENT OF EACH OUTPUT vs NUMBER OF OUTPUTS CONDUCTING SIMULTANEOUSLY N – Number of Outputs Conducting Simultaneously of Each Output – A D I 0 1234 5678 V CC = 5 V T C = 25°C T C = 125°C 0.45 0.4 0.35 0.3 0.25 0.2 0.15 0.1 0.05 T C = 100°C Figure 11 – Maximum Peak Drain Current of Each Output – A MAXIMUM PEAK DRAIN CURRENT OF EACH OUTPUT vs NUMBER OF OUTPUTS CONDUCTING SIMULTANEOUSLY D N – Number of Outputs Conducting Simultaneously I 0.15 0.05 0.4 0 12 34 5 0.3 0.2 0.35 0.5 678 0.45 0.25 0.1 V CC = 5 V T C = 25°C d = t w /t period = 1 ms/t period d = 10% d = 20% d = 50% d = 80% IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. 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OUT 2 NC – No internal connection TPIC6B595 POWER LOGIC 8-BIT SHIFT REGISTER SLIS032 – JULY 1995 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 logic diagram (positive logic) G RCK SRCLR SRCK SER. TABLE PACKAGE T C ≤ 25°C POWER RATING DERATING FACTOR ABOVE T C = 25°C T C = 125°C POWER RATING DW 1389 mW 11.1 mW/°C 278 mW N 1050 mW 10.5 mW/°C 263 mW TPIC6B595 POWER LOGIC 8-BIT SHIFT REGISTER SLIS032. storage register. Data transfers through both the shift and storage registers on the rising edge of the shift- register clock (SRCK) and the register clock (RCK), respectively. The storage register transfers