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TON DUC THANG UNIVERSITY FACULTY OF ELECTRICAL-ELECTRONICS ENGINEERING DIVISION OF ELECTRONICS-TELECOMMUNICATIONS DIGITAL FUNDAMENTAL Laboratory Manual Source: Lab-Volt Systems, Inc Edited by Division of Electronics-Telecommunication Table of Contents Unit - Fundamental Logic Elements EXERCISE 1-1: AND/NAND Logic Functions EXERCISE OBJECTIVE DISCUSSION PROCEDURE 11 REVIEW QUESTIONS 14 EXERCISE 1-2: OR/NOR Logic Functions 15 EXERCISE OBJECTIVE 15 DISCUSSION 15 PROCEDURE 18 REVIEW QUESTIONS 21 Unit - EXCLUSIVE-OR/NOR Gates 22 EXERCISE 2-1: EXCLUSIVE-OR (-NOR) Gate Functions 24 EXERCISE OBJECTIVE 24 DISCUSSION 24 PROCEDURE 25 REVIEW QUESTIONS 27 EXERCISE 2-2: Dynamic Response of XOR/ XNOR Logic Gates 28 EXERCISE OBJECTIVE 28 DISCUSSION 28 PROCEDURE 30 REVIEW QUESTIONS 31 Unit - Flip-Flops 32 EXERCISE 3-1: S/R Flip-Flop 35 EXERCISE OBJECTIVE 35 DISCUSSION 35 PROCEDURE 38 REVIEW QUESTIONS 41 EXERCISE 3-2: D Flip-Flop 42 EXERCISE OBJECTIVE 42 DISCUSSION 42 PROCEDURE 44 REVIEW QUESTIONS 47 Unit - JK Flip-Flop 48 EXERCISE 4-1: Static Operation 51 PROCEDURE 51 REVIEW QUESTIONS 54 EXERCISE 4-2: Dynamic Operation 55 EXERCISE OBJECTIVE 55 DISCUSSION 55 PROCEDURE 57 REVIEW QUESTIONS 59 Unit - The MULTIPLEXER and DEMULTIPLEXER 60 EXERCISE 5-1: MULTIPLEXER 66 EXERCISE OBJECTIVE 66 DISCUSSION 66 PROCEDURE 68 REVIEW QUESTIONS 70 EXERCISE 5-2: DEMULTIPLEXER 71 EXERCISE OBJECTIVE 71 DISCUSSION 71 PROCEDURE 74 REVIEW QUESTIONS 76 Unit - ASYNCHRONOUS RIPPLE COUNTER 77 EXERCISE 6-1: Basic Counter Control Functions 79 EXERCISE OBJECTIVE 79 DISCUSSION 79 PROCEDURE 82 REVIEW QUESTIONS 84 EXERCISE 6-2: Ripple Counter Waveforms 85 EXERCISE OBJECTIVE 85 DISCUSSION 85 PROCEDURE 87 REVIEW QUESTIONS 89 Unit - 4-BIT COMPARATOR 90 EXERCISE 7-1: Fundamental Binary Comparisons 94 EXERCISE OBJECTIVE 94 DISCUSSION 94 PROCEDURE 96 REVIEW QUESTIONS 99 EXERCISE 7-2: Comparators And Counter Modulus Control 100 EXERCISE OBJECTIVE 100 DISCUSSION 100 PROCEDURE 102 REVIEW QUESTIONS 104 Unit - Fundamental Logic Elements UNIT OBJECTIVE At the completion of this unit, you will be able to determine the input/output relationship of logic elements on the DIGITAL LOGIC FUNDAMENTALS circuit board DISCUSSION OF FUNDAMENTALS In TTL digital circuits, there are two fundamental voltage levels, or logic states: a high state, called a logic high and equal to +5 Vdc, and a low state, called a logic low and equal to volts For practical circuits, each state consists of a minimum and a maximum voltage level Outside of this range, the logic circuit cannot reliably determine which logic state to assign Figure 1-1 illustrates the operating limits of typical TTL circuits Figure 1-1 Operating levels of TTL circuits In the figure, a voltage level between 0.8 and volts represents an unknown logic state Logic levels that operate near the threshold can generate intermittent results because any noise that adds to the signal will move the input of the gate to the unknown logic state Logic high values, represented by 1, range between and Vdc Logic low values, represented by 0, range between zero and 0.8 Vdc Ones (1) and zeros (0) are used to define the operational tables of standard logic gates and circuits Figure 1-2 illustrates two fundamental logic concepts Figure 1-2 Logic Concepts In Figure 1-2(a), switches A and B must be closed to illuminate the lamp Switch A AND switch B must be activated If either switch is opened (not activated), the lamp goes off In Figure 1-2(b), either switch A or switch B can be closed to illuminate the lamp Switch A OR switch B must be activated Both switches must be opened (not activated) to turn the lamp off Switch positions can be related to logic levels Logic levels are represented by highs (1) or lows (0); therefore, the standard AND and OR logic functions can be stated with highs and lows (ones and zeros) This relationship is illustrated by Table 1-1 Table 1-1 Switch state OFF ON Logic Level State LOW HIGH Boolean equations used to define the input/ output relationships of logic circuits In place of ones and zeros, Boolean equations take the form of A and B = C Figure 1-3 illustrates this circuit notation Figure 1-3 Boolean form of notation In the figure, the Boolean equation A and B = C defines the circuit operation The expression states that both switches A and B must be activated (on or high) to illuminate the lamp (C) If a lamp-on condition is considered a logic high, then both A and B must be high to generate a high output Basic logic functions can be complemented The complement of a logic state is its opposite state Logic high and low levels (1 and 0) are complements of each other Zero (0) is the ones complement of one (1), while is the ones complement of The complexity of an IC package determines its classification In general, IC packages having 12 or less logic gates are classified as Small Scale Integration (SSI) devices IC classification types range from SSI to Very Large Scale Integration (VLSI) and beyond The relationship between gate count and classification is illustrated in Figure 1-4 Figure 1-4 IC classification and gate count EXERCISE 1-1: AND/NAND Logic Functions EXERCISE OBJECTIVE When you have completed this exercise, you will be able to determine the operation of an AND and a NAND logic gate You will verify your results by generating truth tables for each function DISCUSSION Figure 1-5 shows the schematic symbols of two-input AND and NAND gates Figure 1-5 AND and NAND gates Signal inputs are labeled A and B Gate outputs are labeled C The output of the NAND gate is the complement of the AND operation The Boolean equation for the AND gate states that C is high when A and B are high The AND operation is indicated by the dot between A and B NOTE: A·B and AB without the "·" are identical The Boolean equation for the NAND gate states that C is low when A and B are high The bar over AB represents the complement of AB The NAND gate function has a bubble drawn at the output side of the gate This bubble indicates a complement Figure 1-6 shows the pin-out configuration for the 74LS00 NAND, SSI IC used in this exercise Figure 1-6 74LS00 NAND, SSI IC In the figure, pins 14 and supply power to the IC The IC provides four separate two-input NAND gates, labeled A through D Each gate provides one output For the 74LS00 IC, inputs may be tied to other inputs or outputs may be connected to inputs; however, outputs cannot be connected to one another Unused inputs generally are pulled high (connected to Vcc) through a pull-up The nominal value of pullup resistors used in LS devices is 18 K-Ohms Two NAND gates can be cascaded (connected in series) to generate an AND operation This configuration is represented by Figure 1-7 Figure 1-7 AND gate operation In the figure, output C provides a NAND response to the circuit inputs (A and B) Output C is complemented by the action of GATES and In turn, these gates generate AND operations (outputs D and E) for the same circuit inputs (A and B) Table 1-2 provides the circuit truth table Table 1-2 Inputs B 1 0 A 1 Outputs NAND AND C D or E 1 1 In the table, the outputs are complements of each other Output column C provides the NAND function truth table, and output columns D and E provide the AND function truth table There are two circuit inputs (A and B) Four unique input conditions test all possible combinations A low level at any input disables an AND or a NAND gate A high level at one input of a two-input AND or NAND gate enables the gate Figure 1-8 illustrates the disable and enable combinations for an AND and a NAND gate Figure 1-8 AND/NAND gate control combinations The truth tables in the figure show that a disabled AND gate locks out its other input and generates a low level (0) output A disabled NAND gate also locks out its other input but generates a high level (1) output Enabled AND or NAND gates allow their outputs to be determined by the circuit inputs, as demonstrated in Figure 1-8 The operating principles of a two-input AND or NAND gate apply to gates having more than two inputs Figure 1-9 shows an eight-input NAND gate (74LS30) NOTE: Remember that a high logic level turns on an LED You can verify the state of a signal, as indicated by a circuit LED, by connecting your multimeter to the appropriate test point Figure 1-9 8-input NAND gate The output of this gate is low only when all inputs are high Any input at a low level locks out the other inputs (and output is high) 10