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Bộ môn Điện tử số do Thầy Nam phó viên trưởng trường ĐHBKHN biên soạn đem lại cho các bạn 1 cách tiếp cận đơn giản dễ hiểu với môn này
Digital Electronics Digital Electronics Dr. Pham Ngoc Nam © R.Lauwereins Imec 2001 Digital design Combina- torial circuits Sequential circuits FSMD design VHDL 1/2 Acknowledgement Acknowledgement • The main part of the slides was adopted and modified from the original slides of Prof. Rudy Lauwereins, Vice president of IMEC, Leuven, Belgium with his permission. © R.Lauwereins Imec 2001 Digital design Combina- torial circuits Sequential circuits FSMD design VHDL Your instructor • Bộ môn kỹ thuật điện tử tin học Office: C9-401 Email: nam.phamngoc@hust.edu.vn, phamngocnam@gmail.com Course email: https://sites.google.com/site/setdigitaldesign/ • Research: FPGA, hệ nhúng Trí tuệ nhân tạo Embedded Systems and Reconfigurable Computing Lab • Education: K37 điện tử-ĐHBK Hà nội (1997) Master về trí tuệ nhân tạo 1999, Đại học K.U. Leuven, vương quốc Bỉ Đề tài: Nhận dạng chữ viết tay Tiến sỹ kỹ thuật chuyên ngành điện tử-tin học, 9/ 2004, Đại học K.U. Leuven-IMEC, Vương Quốc Bỉ Đề tài: quản lý chất lượng dịch vụ trong các ứng dụng đa phương tiện tiên tiến © R.Lauwereins Imec 2001 Digital design Combina- torial circuits Sequential circuits FSMD design VHDL 1/4 Course contents Course contents • Digital design • Combinatorial circuits: without status • Sequential circuits: with status • FSMD design: hardwired processors • Language based HW design: VHDL © R.Lauwereins Imec 2001 Digital design Combina- torial circuits Sequential circuits FSMD design VHDL 1/5 Course contents Course contents Digital design • Combinatorial circuits: without status • Sequential circuits: with status • FSMD design: hardwired processors • Language based HW design: VHDL © R.Lauwereins Imec 2001 Digital design Combina- torial circuits Sequential circuits FSMD design VHDL 1/6 Contents of “Digital Design” Contents of “Digital Design” • Introduction to the course • Data representation • Boolean algebra • Logical gates © R.Lauwereins Imec 2001 Digital design Combina- torial circuits Sequential circuits FSMD design VHDL 1/7 Contents of “Digital Design” Contents of “Digital Design” • Introduction to the course Course book Goal Exercises and laboratory sessions Exam • Data representation • Boolean algebra • Logical gates © R.Lauwereins Imec 2001 Digital design Combina- torial circuits Sequential circuits FSMD design VHDL 1/8 Contents of “Digital Design” Contents of “Digital Design” • Introduction to the course Course book Goal Exercises and laboratory sessions Exam • Data representation • Boolean algebra • Logical gates © R.Lauwereins Imec 2001 Digital design Combina- torial circuits Sequential circuits FSMD design VHDL 1/9 Course books Course books • Mandatory: “Principles of Digital Design”, Daniel D. Gajski, Prentice Hall, 1997, ISBN 0-13-301144-5 • References: Douglas L. Perry, VHDL: Programming by Examples, McGraw- Hill, fourth Edition, 2002. “Logic and Computer Design Fundamentals”, M. Morris Mano & Charles R. Kime, Prentice Hall, 2nd edition, 2000, ISBN 0- 13-016176-4 TS. Nguyễn Nam Quân : “Toán logic và Kỹ thuật số”, Nhà xuất bản khoa học và kỹ thuật, 2006 © R.Lauwereins Imec 2001 Digital design Combina- torial circuits Sequential circuits FSMD design VHDL 1/10 Contents of “Digital Design” Contents of “Digital Design” • Introduction to the course Course book Goal Exercises and laboratory sessions Exam • Data representation • Boolean algebra • Logical gates [...]... -1 0 1 2 3 4 5 6 7 10 00 10 01 1 010 10 11 110 0 11 01 111 0 11 11 0000 00 01 0 010 0 011 010 0 010 1 011 0 011 1 11 11 111 0 11 01 110 0 10 11 1 010 10 01 1000 & 0000 00 01 0 010 0 011 010 0 010 1 011 0 011 1 Negating a 2-complement number requires many more bit-flips than negating a sign-magnitude number: sign-magnitude is less power hungry than 2-complement Two’s complement addition and subtraction © R.Lauwereins Imec 20 01. .. 010 0 +4 + 00000 011 0 +6 0 010 +2 11 00 - 4 + 00000 11 10 - 2 11 10 - 2 11 00 - 4 + 11 000 10 10 - 6 0 010 +2 0 011 (- 4)’ + 0 011 1 011 0 +6 11 10 - 2 0 011 (- 4)’ + 11 111 0 010 +2 Subtraction 0 010 +2 10 11 (+4)’ + 0 011 1 11 10 - 2 Overflow 1/ 35 011 1 +7 011 0 +6 + 011 00 11 01 - 3 10 01 - 7 10 10 - 6 + 10 000 0 011 +3 © R.Lauwereins Imec 20 01 Digital design Contents of “Digital Design” • • FSMD design VHDL 1/ 36 Data representation... circuits 11 01 111 0 Sequential circuits 0000 11 10 FSMD design 11 10 VHDL 10 110 110 • • 1/ 25 Multiplication by repeated add & shift: number of cycles = number of bits of multiplier Can be implemented in a faster way © R.Lauwereins Imec 20 01 Binary division Digital design 10 111 010 11 10 Combinatorial circuits 10 010 10 11 10 11 01 111 0 Sequential circuits 10 010 0000 FSMD design 10 010 VHDL 11 10 10 0 • • 1/ 26 Division... 010 x 562 sum • 8273 y Sequential circuits FSMD design Decimal addition 8835 Binary addition carry 0 011 111 x y 10 1 011 1 sum 1/ 23 10 011 011 11 110 010 © R.Lauwereins Imec 20 01 Binary subtraction Digital design Combinatorial circuits Sequential circuits FSMD design VHDL 1/ 24 x 11 1 01 y 11 11 borrow result 11 10 011 10 © R.Lauwereins Imec 20 01 Binary multiplication Digital design 11 10 Combinatorial circuits 11 01. .. 12 34.56 710 = 1 10 00+2 10 0+3 10 +4 1+ 5•0 .1+ 6•0. 01+ 7•0.0 01 1 10 3+2 10 2+3 10 1+4 10 0+5 10 -1+ 6 10 -2+7 10 -3 r = radix (r = 10 ), d=digit (0 ≤ d ≤ 9), m = #digits before radix point (decimal point), n = #digits after decimal point Sequential circuits FSMD design VHDL 1/ 18 D= m 1 ∑d i=− n i •r i © R.Lauwereins Imec 20 01 Digital design Combinatorial circuits Binary • 10 11. 011 2= 1 8+0•4 +1 2 +1 1+ 0•0.5 +1 0.25 +1 0 .12 5... VHDL 1/ 20 O= m 1 ∑d i=− n i •8 i © R.Lauwereins Imec 20 01 Digital design Combinatorial circuits Hexadecimal • FEDC.7 616 = 15 •4096 +14 •256 +13 16 +12 1+ 7 1/ 16+6 1/ 256 15 16 3 +14 16 2 +13 16 1 +12 16 0+7 16 -1+ 6 16 -2 r = radix (r = 16 ), d = digit (0 ≤ d ≤ F), m = #digits before radix point (hexadecimal point), n = #digits after radix point Sequential circuits FSMD design VHDL 1/ 21 H= m 1 ∑d i =− n i • 16 ... 2-complement of 11 012 is 0 010 2 + 00 012 = 0 011 2 © R.Lauwereins Imec 20 01 Digital design Combinatorial circuits Sequential circuits FSMD design VHDL 1/ 32 Two’s complement notation • • • • • How do we negate a number D, i.o.w how do we obtain -D? m m D* = r - D ⇒ D* + D = r = 0 when we retain only the m least significant digits ⇒ D* = -D eg D=0 011 2 ⇒ D* =11 002+00 012 =11 012 4 D+D*=0 011 2 +11 012 =10 0002=2 =0 when... VHDL 1/ 28 Sign-Magnitude representation • • • • • • Each number consists of two parts : sign and magnitude Decimal example: +12 310 (by convention also 12 3’) and -12 310 Binary: sign represented by MSB; ‘0’ = positive, 1 = negative Binary example: 011 002 = +12 10 en 11 1002 = -12 10 A sign-magnitude integer with n bits lies between -(2 representations for 0: 000 0 en 10 0 0 n -1 n -1 -1) and +(2 -1) with... 1 8+0•4 +1 2 +1 1+ 0•0.5 +1 0.25 +1 0 .12 5 1 23+0•22 +1 21+ 1•20+0•2 -1+ 1•2-2 +1 2-3 r = radix (r = 2), d = digit (0 ≤ d ≤ 1) , m = #digits before radix point (binary point), n = #digits after radix point Sequential circuits FSMD design VHDL 1/ 19 B= m 1 ∑d i=− n i •2 i © R.Lauwereins Imec 20 01 Digital design Combinatorial circuits Octal • 7654.328= 7• 512 +6•64+5•8+4 1+ 3•0 .12 5+2•0. 015 625 7•83+6•82+5• 81+ 4•80+3•8 -1+ 2•8-2 ... complement notation © R.Lauwereins Imec 20 01 Digital design Combinatorial circuits Sequential circuits FSMD design VHDL 1/ 31 Two’s complement notation • • • • • Radix-complement of a number D with m digits is D* = r m -D eg The 10 -complement of 12 310 is 3 10 - 12 310 = 87 710 eg The 2-complement of 11 012 is 4 2 - 13 10 = 310 = 0 011 2 Call D’ the digit complement, then D*=D’ +1 (proof in book); this offers us an . 20 01 Digital design Combina- torial circuits Sequential circuits FSMD design VHDL 1/ 19 Binary Binary • 10 11. 011 2= 1 8+0•4 +1 2 +1 1+ 0•0.5 +1 0.25 +1 0 .12 5 1 2 3 +0•2 2 +1 2 1 +1 2 0 +0•2 -1 +1 2 -2 +1 2 -3 r. 20 01 Digital design Combina- torial circuits Sequential circuits FSMD design VHDL 1/ 18 Decimal Decimal • 12 34.56 710 = 1 10 00+2 10 0+3 10 +4 1+ 5•0 .1+ 6•0. 01+ 7•0.0 01 1 10 3 +2 10 2 +3 10 1 +4 10 0 +5 10 -1 +6 10 -2 +7 10 -3 r. 20 01 Digital design Combina- torial circuits Sequential circuits FSMD design VHDL 1/ 20 Octal Octal • 7654.328= 7• 512 +6•64+5•8+4 1+ 3•0 .12 5+2•0. 015 625 7•8 3 +6•8 2 +5•8 1 +4•8 0 +3•8 -1 +2•8 -2 r = radix (r = 8), d = digit (0