ECE 410, Prof. A. Mason Lecture Notes 7.1 CMOS Inverter: DC Analysis • Analyze DC Characteristics of CMOS Gates by studying an Inverter • DC Analysis – DC value of a signal in static conditions • DC Analysis of CMOS Inverter –Vin, input voltage – Vout, output voltage – single power supply, VDD – Ground reference –find Vout = f(Vin) • Voltage Transfer Characteristic (VTC) – plot of Vout as a function of Vin – vary Vin from 0 to VDD – find Vout at each value of Vin ECE 410, Prof. A. Mason Lecture Notes 7.2 Inverter Voltage Transfer Characteristics • Output High Voltage, V OH – maximum output voltage • occurs when input is low (Vin = 0V) • pMOS is ON, nMOS is OFF • pMOS pulls Vout to VDD –V OH = VDD • Output Low Voltage, V OL – minimum output voltage • occurs when input is high (Vin = VDD) • pMOS is OFF, nMOS is ON • nMOS pulls Vout to Ground –V OL = 0 V •Logic Swing – Max swing of output signal •V L = V OH -V OL •V L = VDD ECE 410, Prof. A. Mason Lecture Notes 7.3 Inverter Voltage Transfer Characteristics • Gate Voltage, f(Vin) –V GSn =Vin, V SGp =VDD-Vin • Transition Region (between V OH and V OL ) –Vinlow •Vin< Vtn –Mnin Cutoff, OFF – Mp in Triode, Vout pulled to VDD •Vin> Vtn< ~Vout – Mn in Saturation, strong current – Mp in Triode, V SG & current reducing – Vout decreases via current through Mn – Vin = Vout (mid point) ≈ ½VDD – Mn and Mp both in Saturation – maximum current at Vin = Vout –Vinhigh • Vin > ~Vout, Vin < VDD - |Vtp| – Mn in Triode, Mp in Saturation • Vin > VDD - |Vtp| –Mnin Triode, Mp in Cutoff + V GSn - + V SGp - Vin < V IL input logic LOW Vin > V IH input logic HIGH •Drain Voltage, f(Vout) –V DSn =Vout, V SDp =VDD-Vout ECE 410, Prof. A. Mason Lecture Notes 7.4 Noise Margin •Input Low Voltage, V IL – Vin such that Vin < V IL = logic 0 – point ‘a’ on the plot •where slope, • Input High Voltage, V IH – Vin such that Vin > V IH = logic 1 – point ‘b’ on the plot •where slope =-1 • Voltage Noise Margins – measure of how stable inputs are with respect to signal interference –VNM H = V OH -V IH = VDD - V IH –VNM L = V IL -V OL = V IL – desire large VNM H and VNM L for best noise immunity 1−= ∂ ∂ Vout Vin ECE 410, Prof. A. Mason Lecture Notes 7.5 Switching Threshold • Switching threshold = point on VTC where Vout = Vin – also called midpoint voltage, V M – here, Vin = Vout = V M • Calculating V M –at V M , both nMOS and pMOS in Saturation – in an inverter, I Dn = I Dp , always! – solve equation for V M – express in terms of V M – solve for V M DptpSGp p tnGSn n tnGSn OXn Dn IVVVVVV L WC I =−=−=−= 222 )( 2 )( 2 )( 2 β βμ 22 )( 2 )( 2 tpMDD p tnM n VVVVV −−=− β β ⇒ tpMDDtnM p n VVVVV −−=− )( β β p n p n tntp M VVVDD V β β β β + +− = 1 ECE 410, Prof. A. Mason Lecture Notes 7.6 Effect of Transistor Size on VTC •Recall • If nMOS and pMOS are same size –(W/L)n = (W/L)p –Coxn= Coxp(always) •If • Effect on switching threshold –if β n ≈β p and Vtn = |Vtp|, V M = VDD/2, exactly in the middle • Effect on noise margin –if β n ≈β p , V IH and V IL both close to V M and noise margin is good L W k nn '= β p p n n p n L W k L W k ⎟ ⎠ ⎞ ⎜ ⎝ ⎛ ⎟ ⎠ ⎞ ⎜ ⎝ ⎛ = ' ' β β p n p n tntp M VVVDD V β β β β + +− = 1 32or L W C L W C p n p oxpp n oxnn p n ≅= ⎟ ⎠ ⎞ ⎜ ⎝ ⎛ ⎟ ⎠ ⎞ ⎜ ⎝ ⎛ = μ μ μ μ β β 1, = ⎟ ⎠ ⎞ ⎜ ⎝ ⎛ ⎟ ⎠ ⎞ ⎜ ⎝ ⎛ = p n n p p n then L W L W β β μ μ since L normally min. size for all tx, can get betas equal by making Wp larger than Wn ECE 410, Prof. A. Mason Lecture Notes 7.7 Example •Given – k’n = 140uA/V 2 , Vtn = 0.7V, VDD = 3V – k’p = 60uA/V 2 , Vtp = -0.7V •Find – a) tx size ratio so that V M = 1.5V –b) V M if tx are same size transition pushed lower as beta ratio increases ECE 410, Prof. A. Mason Lecture Notes 7.8 CMOS Inverter: Transient Analysis • Analyze Transient Characteristics of CMOS Gates by studying an Inverter • Transient Analysis – signal value as a function of time • Transient Analysis of CMOS Inverter – Vin(t), input voltage, function of time – Vout(t), output voltage, function of time – VDD and Ground, DC (not function of time) – find Vout(t) = f(Vin(t)) • Transient Parameters –output signal rise and fall time – propagation delay ECE 410, Prof. A. Mason Lecture Notes 7.9 Transient Response • Response to step change in input – delays in output due to parasitic R & C •Inverter RC Model – Resistances –Rn= 1/[β n (V DD -Vtn)] –Rp= 1/[β n (V DD -|Vtp|)] –Output Cap. (only output is important) •C Dn (nMOS drain capacitance) –C Dn = ½ Cox W n L + C j A Dnbot + C jsw P Dnsw •C Dp (pMOS drain capacitance) –C Dp = ½ Cox W p L + C j A Dpbot + C jsw P Dpsw • Load capacitance, due to gates attached at the output –C L = 3 Cin = 3 (C Gn + C Gp ), 3 is a “typical” load • Total Output Capacitance –Cout= C Dn + C Dp + C L + Vout - C L term “fan-out” describes # gates attached at output ECE 410, Prof. A. Mason Lecture Notes 7.10 Fall Time • Fall Time, t f – time for output to fall from ‘1’ to ‘0’ –derivation: • initial condition, Vout(0) = VDD • solution – definition •t f is time to fall from 90% value [V 1 ,t x ] to 10% value [V 0 ,t y ] •t f = 2.2 τ n n outout out R V t V Ci = ∂ ∂ −= n t DD eVtVout τ − =)( τ n = R n C out time constant ⎟ ⎠ ⎞ ⎜ ⎝ ⎛ = Vout V t DD n ln τ ⎥ ⎦ ⎤ ⎢ ⎣ ⎡ ⎟ ⎟ ⎠ ⎞ ⎜ ⎜ ⎝ ⎛ − ⎟ ⎟ ⎠ ⎞ ⎜ ⎜ ⎝ ⎛ = DD DD DD DD n V V V V t 9.0 ln 1.0 ln τ [...]... these cases ECE 410, Prof A Mason Lecture Notes 7.17 Series/Parallel Equivalent Circuits • Scale both W and L – no effective change in W/L – increases gate capacitance β = μCox (W/L) inputs must be at same value/voltage • Series Transistors – increases effective L effective β⇒½β • Parallel Transistors – increases effective W effective β ⇒ 2β ECE 410, Prof A Mason Lecture Notes 7.18 NAND: DC Analysis •... ⇓W, (⇓Cj, ⇓Cox ) • Delay ∝ Cout(Rn+Rp) ∝ L W L W VDD = L2 VDD Decreasing L (reducing feature size) is best way to improve speed! ECE 410, Prof A Mason Lecture Notes 7.14 Switching Speed -Local Modification • Previous analysis applies to the overall design – shows that reducing feature size is critical for higher speed – general result useful for creating cell libraries • How do you improve speed within... rise and fall propagation delays for total value ECE 410, Prof A Mason Lecture Notes 7.12 Switching Speed -Resistance • Rise & Fall Time τn = RnCout – tf = 2.2 τn, tr = 2.2 τp, • Propagation Delay Rn = 1/[βn(VDD-Vtn)] – tp = 0.35(τn + τp) Cout = CDn + CDp + CL – delay ∝ τn + τp – τn + τp = Cout (Rn+Rp) • Define delay in terms of design parameters – Rn+Rp = (VDD-Vt)(βn +βp) βn βp(VDD-Vt)2 βn + βp Beta... all series transistor go from OFF to ON – and all internal caps have to be • charged (NOR) • discharged (NAND) ECE 410, Prof A Mason Lecture Notes 7.25 Performance Considerations • Speed based on βn, βp and parasitic caps • DC performance (VM, noise) based on βn/βp • Design for speed not necessarily provide good DC performance • Generally set tx size to optimize speed and then test DC characteristics... increases chip area needed, which is bad • fast circuits need more chip area (chip “real estate”) • Increasing VDD is not a good choice because it increases power consumption ECE 410, Prof A Mason Lecture Notes 7.15 CMOS Power Consumption • P = PDC + Pdyn – PDC: DC (static) term – Pdyn: dynamic (signal changing) term • PDC – P = IDD VDD • IDD DC current from power supply • ideally, IDD = 0 in CMOS:... = VDD Qe f = Cout VDD2 f, f = frequency of signal change Power increases with Cout and frequency, and strongly with Total Power, P = IDDQ VDD + Cout VDD2 f VDD (second order) ECE 410, Prof A Mason Lecture Notes 7.16 Multi-Input Gate Signal Transitions • In multi-input gates multiple signal transitions produce output changes • What signal transitions need to be analyzed? – for a general N-input gate... β= μCox (W/L) Rp = 1/[βp(VDD-|Vtp|)] • In General – Rn+Rp = τp = RpCout if Wn=Wp=W, and L=Ln=Lp L (μn+ μp) (μn μp) Cox W (VDD-Vt) To decrease R’s, ⇓L, ⇑W, ⇑VDD, ( ⇑μp, ⇑Cox ) ECE 410, Prof A Mason Lecture Notes 7.13 Switching Speed -Capacitance • From Resistance we have – ⇓L, ⇑W, ⇑VDD, ( ⇑μp, ⇑Cox ) Cout = CDn + CDp + CL if L=Ln=Lp – but ⇑ VDD increases power – ⇑ W increases Cout estimate CL = 3 (CGn... same L • VM = VA = VB = Vout – can merge transistors at this point • if WpA=WpB and WnA=WnB – series nMOS, βN ⇒ ½ βn – parallel pMOS, βP ⇒ 2 βp – can now calculate the NAND VM ECE 410, Prof A Mason Lecture Notes 7.19 NAND Switching Point • Calculate VM for NAND – 0,0 to 1,1 transition • all tx change states (on, off) • in other transitions, only 2 change – VM = VA = VB = Vout – set IDn = IDp, solve for... with N inputs VDD − Vtp + Vtn VM = 1 1+ N 1 N βn βp βn βp to balance this effect and set VM to VDD/2, can increase β by increasing Wn but, since μn>μp, VM≈VDD/2 when Wn = Wp ECE 410, Prof A Mason Lecture Notes 7.20 NOR: DC Analysis • Similar Analysis to NAND • Critical Transition – 0,0 to 1,1 – when all transistors change • VM for NOR2 critical transition – if WpA=WpB and WnA=WnB • parallel nMOS, βn... VDD − Vtp + NVtn VM = 1+ N βn βp βn βp for NOR-N – series pMOS resistance means slower rise – VTC shifted to the left – to set VM to VDD/2, increase Wp • this will increase βp ECE 410, Prof A Mason Lecture Notes 7.21 NAND: Transient Analysis • NAND RC Circuit – R: standard channel resistance – C: Cout = CL + CDn + 2CDp • Rise Time, tr – Worst case charge circuit • 1 pMOS ON – tr = 2.2 τp • τp = Rp Cout . way to improve speed! ECE 410, Prof. A. Mason Lecture Notes 7.15 Switching Speed -Local Modification • Previous analysis applies to the overall design – shows that reducing feature size is critical. function of Vin – vary Vin from 0 to VDD – find Vout at each value of Vin ECE 410, Prof. A. Mason Lecture Notes 7.2 Inverter Voltage Transfer Characteristics • Output High Voltage, V OH – maximum output. V •Logic Swing – Max swing of output signal •V L = V OH -V OL •V L = VDD ECE 410, Prof. A. Mason Lecture Notes 7.3 Inverter Voltage Transfer Characteristics • Gate Voltage, f(Vin) –V GSn =Vin, V SGp =VDD-Vin •