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Analog BiCMOS design practices and pitfalls
[...]... are occupying states in the valence band The difference between the conduction band edge and the valence band edge is EG = 1.12 eV , the band gap When a silicon atom loses an electron, it takes 1.12 electron volts of energy for the electron to move from the valence to the conduction band When this happens the conduction band is occupied by an electron and the valence band is occupied by a hole Impurities... the valence and conduction bands This Fermi level is called the intrinsic level, Ei In an n-type semiconductor, with conduction band states occupied, the Fermi level moves up closer to the conduction band as the probability that a conduction band state is occupied increases In p-type semiconductors, with vacant valance band states (holes), the Fermi level moves down closer to the valence band The position... hole Impurities introduce electron states inside the band gap close to the valence or conduction band Donor states are close to the conduction band It takes very little energy for an electron to move from a donor state to the conduction band Acceptor states are located close to the valence band A valence electron can easily move from the valence band to an acceptor state The Fermi level is a measure... conduction band is n2 /NA Conduction band states in the n-side are 1 occupied but conduction band states in the p-side tend to be unoccupied Boltzmann’s Equation 1.30 can be used to find the relationship between the densities of conduction electrons on the n-sides and p-sides of the junction and the junction built-in potential Let N1 equal the density of conduction electrons on the p-side of the junction and. .. can be occupied by electrons are limited to bands of energy in silicon as shown in Figure 1.3 The valence band is normally Figure 1.2 Carrier mobility in silicon at 300 ◦ K decreases significantly with impurity concentration.[1] (Reprinted from Solid-State Electronics, Volume II, S M Sze and J C Irvin, Resistivity, Mobility and Impurity Levels in GaAs, Ge, and Si at 300◦ K., pages 599-602, Copyright... across the depletion region is found at x = 0 and has a value Emax = − where qNA xp is the permittivity of silicon =− qND xn (1.18) We have assumed the depletion region and junction boundaries are sharp and well defined Defining the potential between x = −xp and x = 0 as V1 0 qNA x2 p V1 = − Edx = (1.19) 2 −xp Similarly, if we define the potential between x = 0 and x = xn as V2 , we obtain xn qND x2 n V2... to move about the crystal occupy states in the conduction band Valence electrons attached to silicon atoms occupy the valence band The intrinsic level is approximately half way between the conduction and valence bands The Fermi level shown corresponds to n-type silicon occupied by valence electrons attached to silicon atoms The conduction band is occupied by conduction electrons that are free to move... width of the collector, and Ndc is the collector doping Rewriting Equations 1.56, 1.57, and 1.58 using constants, A, B, C, where AE qDn n2 i A= WB NA B= AE qDpe n2 i WE Nde C= AC qDpc n2 i Wepi Ndc Using the constants A, B, and C in Equations 1.56, 1.57, and 1.58: Vbe Vbc Inc = A e VT − e VT Vbe Ipe = B e VT − 1 (1.59) Vbc Ipc = C e VT − 1 Plugging Equations 1.59 into Equations 1.53 and 1.54: Vbe Vbc IE... where µn and E are the electron mobility and the electric field Mobility decreases when there is more scattering of carriers Lattice scattering increases with temperature Therefore, mobility and conductivity tend to decrease with temperature Carriers are also scattered from impurities Mobility decreases significantly with doping as shown in Figure 1.2.[2] Conductivity is proportional to mobility and carrier... voltage across the junction exists across xn , and is approximately Ψo + VR ≈ V2 Also, from Equations 1.23 and 1.18, the width of the depletion region and the maximum electric field are xd ≈ xn = Emax = 2 (Ψo + VR ) qND 2qND (Ψo + VR ) (1.24) (1.25) The width of the depletion region is an important parameter for the calculation of junction capacitance and the “punch through” breakdown voltage The maximum . Semiconductor Corp. Practices and Pitfalls Analog BiCMOS DESIGN