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ASIC and FPGA verification a guide to component modeling morgan kaufmann
[...]... values used in the constraints and delays are external to the actual models and are applied to the simulation through SDF annotation The intent of this book is show how ASICs and FPGAs can be verified in the larger context of a board or system To improve readability, the phrase “ASICs and FPGAs” will be abbreviated to just FPGAs However, nearly everything said about FPGA verification applies equally to. .. examples in this book are taken from the FMF Web site Structure of the Book ASIC and FPGA Verification: A Guide to Component Modeling is organized so that it can be read linearly from front to back Chapters are grouped into four parts: Introduction, Resources and Standards, Modeling Basics, and Advanced Modeling Each part covers a number of related modeling concepts and techniques, with individual chapters... the gate-level netlist They are provided in libraries by FPGA vendors and are usually specific to a particular FPGA family Cell models include propagation delays and timing constraints However, the actual delay and constraint values are not coded directly into the models Instead, these values are calculated by software usually provided by the FPGA vendor The calculated values are then written to an SDF... abstraction Small groups of transistors are used to design simple digital circuits like gates and registers These are small enough to be easily simulated in the analog domain and measured in the lab The results of the analog simulations are used to assign overall properties, such as propagation delays and timing constraints to the gates This is referred to as characterization The characterized gates can then... simulator The EDA companies backing VHDL saw they had to do something The something was named VITAL, the VHDL Initiative toward ASIC Libraries The VITAL Specification The intent of VITAL was to provide a set of standard practices for modeling ASIC primitives, or macrocells, in VHDL and in the process make acceleration possible Two VHDL packages were written: a primitives package and a timing package The primitives... discusses the importance of consistent formatting and style in component modeling and how they affect maintenance Basic concepts of modeling are introduced This page intentionally left blank C H A P T E R 1 Introduction to Board-Level Verification As large and complex as today’s FPGAs are, they always end up on a board Though it may be called a “system on a chip,” it is usually part of a larger system with... HILO, SILO, and TEGAS Most large corporations, like IBM, had their own internal simulators At the ASIC and later FPGA levels each foundry had to decide which simulators they would support There were too many simulators available for anyone to support them all Each foundry had to validate that the models they provided worked correctly on each supported release of their chosen simulators At the board level,... in greater detail in Chapter 4.) Another stated goal of VITAL is model maintainability It restricts the writer to a subset of the VHDL language and demands consistant use of provided libraries This encourages uniformity among models, making them easily readable by anyone familiar with VITAL Reabability and having the difficult code placed in a provided library greatly facilitate the maintainence of models... differs from an equivalent synthesizable model Part II covers the standards adhered to in component modeling and the many supporting packages that make it practical Chapter 3 covers several IEEE and FMF packages that are used in writing component models Chapter 4 provides an overview of SDF as it applies to component modeling Chapter 5 describes the organization and requirements of VITAL models Chapter 6... applies equally to ASIC verification This book should also be useful to engineers responsible for the generation and maintenance of VITAL libraries used for gate-level simulation of ASICs and FPGAs Component vendors that provide simulation models to their customers are able to take advantage of some important opportunities The more quickly a customer is able to verify a design and get it into production, .