VIETNAM NATIONAL UNIVERSITY – HO CHI MINH CITY UNIVERSITY OF SCIENCE LÊ THỊ LINH AN A SOFT ERROR TOLERANT SRAM DESIGN IN 130NM CMOS TECHNOLOGY Specialization: Electronic Engineering – Microelectronics Major Code: 60 52 70 MASTER DEGREE THESIS ELECTRONICS ENGINEERING – MICROELECTRONICS SUPERVISOR Dr. BÙI TRỌNG TÚ Ho Chi Minh City, 2010 ACKNOWLEDGEMENTS It is my pleasure to thank all the people who made this thesis possible. First of all, I would like to sincerely express my appreciation to my advisor, Dr. Bui Trong Tu, for his tremendous support, valuable guidance and constant encouragement during my studies. His technical advice made my master’s studies a meaningful learning experience. I am also grateful to Prof. Dang Luong Mo, Prof. Nguyen Huu Phuong, and Dr. Huynh Huu Thuan, who are the managers of this Microelectronics Master program. This is really an interesting course with enthusiastic and devoted professors, who are the experts in the IC industry. I also wish to thank my colleagues in TCAM team for all helpful discussion and valuable advice during my study. Appreciation is expressed for Silicon Design Solutions Company who have supported me about financial and let me join in this Master course during my work. Finally, my special thanks to my family who have always been with me throughout the difficulties and challenges of my master study. Ho Chi Minh City, November 2010 Le Thi LinhAn ABSTRACT Soft error is a great concern for microelectronics circuits today. With the advanced development in CMOS technologies, VLSI circuits are becoming more sensitive to external noise sources, especially radiation particle strikes, which are the cause of soft error. Soft errors are random and do not cause the permanent failure. However, it causes the corruption of stored information, which could turn to the failure in functionality of the circuits. Meanwhile, the demand for a higher reliability of electronics applications is always a non-stop requirement. There are a lot of critical applications that need the extreme exactly in circuit functionality, such as the circuits used in space or biomedical equipment, as well as the military electronics and so on. Generally, soft errors in memories attracted more attention than soft errors in logic circuit. In addition, memories play an important part in modern system. Because of the high integration of storage cells, a large memory is more sensitive to particle strikes than logic. Due to that motivation, this thesis focuses to study about soft errors in memories. The thesis goes through the background knowledge of soft errors and its mitigation techniques. Then, a SRAM design with additional soft error tolerant feature will be presented. The SRAM is designed in 130nm CMOS technology, using circuit hardening and error correcting code techniques to mitigate the soft error effect. The soft error tolerant level is verified by some simulations. Not only focus on the soft error tolerant circuits, a whole SRAM architecture will be shown in detail, from circuit to physical implementation. The verification and simulation results are also included. TABLE OF CONTENTS Acknowledgement Abstract Table of contents Abbreviations List of tables List of figures CHAPTER 1 - INTRODUCTION 1 1.1. Problem and motivation 1 1.2. Contribution of the thesis 2 1.3. Thesis organization 2 CHAPTER 2 - BACKGROUND 4 2.1. Soft errors in semiconductor device 4 2.1.1. Radiation sources 4 2.2. Soft errors occurrence mechanism 5 2.3. Soft errors mitigation techniques 6 2.3.1. Device level techniques 6 2.3.2. Circuit level techniques 7 2.3.3. Block level techniques 7 CHAPTER 3 – SOFT ERROR TOLERANT SRAM DESIGN 10 3.1. SRAM specification 10 3.1.1. General information 10 3.1.2. Floorplan 11 3.1.4. Operation brief description 12 3.2. SRAM detail design 14 3.2.1. SRAM cell architecture 14 3.2.2. Replica path for Read operation 15 3.2.3. Internal clock generator 17 3.2.4. Write circuit 19 3.2.5. Decoder 19 3.2.6. Input/output latches 21 3.3. Error detecting and correcting (EDC) block 22 3.3.1. Hamming code algorithm 23 3.3.2. EDC block implementation 24 3.3.3. EDC detail architecture 26 CHAPTER 4 – DESIGN SIMULATION AND VERIFICATION 37 4.1. SRAM cell simulation 37 4.1.1. SRAM cell simulation to find device size 37 4.1.2. SRAM cell characteristic summary 42 4.1.3. Static noise margin comparison 43 4.1.4. SRAM cell capacitance 43 4.2. Soft error tolerant simulation 44 4.2.1. Verification methodology 44 4.2.2. Critical charge simulation 45 4.2.3. Simulation results 46 4.2.4. Conclusion 49 4.3. Post-layout simulation 50 4.3.1. Simulation setup 50 4.3.2. Cycle time definition and simulation result 52 4.3.3. Access time 55 4.3.4. Setup time 56 4.3.5. Timing delay of some critical paths 57 4.3.6. Simulation results summary 61 4.4. SRAM and EDC functional verification 61 4.4.3. Simulation setup 65 4.4.4. Functional verification result 67 4.5. Physical verification 70 CHAPTER 5 – CONCLUSION AND FUTURE WORK 75 ABBREVIATIONS VLSI Very large scale integration CMOS Complementary Metal-Oxide Semiconductor SEU Single Event Upset DRC Design Rule Check LVS Layout versus Schematic SRAM Static Random Access Memory ECC Error Correcting Code EDC Error Detecting and Correcting SNM Static noise margin LPE Layout Parasitic Extraction LIST OF TABLES Table 3.1: Pin description 12 Table 3.2: Hamming code for 22 bits 24 Table 4.1: Read current 38 Table 4.2: Read leakage current 38 Table 4.3: Effect of leakage on read current 38 Table 4.4: Write current 40 Table 4.5: Static noise margin 41 Table 4.6: SRAM cell characteristic summary 43 Table 4.7: SNM comparison 43 Table 4. 8: SRAM cell capacitance 44 Table 4.9: Critical charge result of hardened SRAM cell 46 Table 4.10: Critical charge result for normal SRAM cell 48 Table 4.11: Performance result (SS_125_1.35) 61 Table 4.12: Timing delay between nodes 61 Table 4.13: Design fault model 62 LIST OF FIGURES Figure 2.1: Redundancy 8 Figure 2.2: Concurrent error detection 8 Figure 3.1: SRAM floorplan 11 Figure 3.2: Write operation 13 Figure 3.3: Read operation 13 Figure 3.4: SRAM cell architecture 15 Figure 3.5: Timing scheme for read operation 16 Figure 3.6: Reference IO cell and read circuit 17 Figure 3.7: Read clock generator circuit 18 Figure 3.8: Write clock generator 19 Figure 3.9: Write circuit and sequential waveform 19 Figure 3.10: Row decoder block diagram 20 Figure 3.11: Xdec circuit 21 Figure 3.12: Hardened latch architecture 22 Figure 3.13: EDC block diagram 25 Figure 3.14: Write encoder schematic 27 Figure 3.15: Parity comparison schematic 28 Figure 3.16: Syndrome decoder schematic 29 Figure 3.17: Bit flipper block 30 Figure 3.18: Input select 31 Figure 3.19: Output select and output latch 32 Figure 3.20: Top level layout view 33 Figure 3.21: SRAM cell layout with only device layers shown 34 Figure 3.23: Xdec cell layout 34 Figure 3.22: SRAM cell layout 34 Figure 3.24: Xdec array 1x256 35 Figure 3.25: Control block 35 Figure 3.26: IO array 1x22 36 Figure 4.1: Read current 37 Figure 4.2: Write current 39 Figure 4.3: Inject a current source to an off NMOS drain 45 Figure 4.4: The injected SEU current for hardened SRAM cell 47 Figure 4.5: IBL waveform of hardened SRAM cell 47 Figure 4.6: The exchange state between IBL and IBLX 47 Figure 4.7: The injected SEU current for normal SRAM cell 48 Figure 4.8: IBL waveform of normal SRAM cell 48 Figure 4.9: The exchange state between IBL and IBLX 49 Figure 4.10: A part of LPE netlist containing capacitance value 50 Figure 4.11: A part of LPE netlist containing resistor value 51 Figure 4.12: A part of input waveform for performance simulation 51 Figure 4.13: Hspice option 52 Figure 4.15: Delay from clk rise to resetx rise 53 Figure 4.14: Cycle time must cover the internal clock 53 Figure 4.17: Delay from clk rise to dmrbl rise 54 [...]... neutrons Alpha particles are generated from the radioactive decay process and when they collide with other atoms Because of alpha particles cannot travel a long path in material, atmosphere therefore is not the main source of alpha particles, but an integrated circuit itself Packaging and soldering contain traces of radioactive isotopes, which lead to release the alpha particles as well as other particles... data output Opening latch will let data go through, however, when closed; data will be stored in latch A SEU could flip the state of data stored in latch, lead to an erroneous data Therefore, in this SRAM design, latches are hardened to duplicate some sensitive nodes All the latches in the design, include address input latch, data input latch and output latch are applied this techniques CHAPTER 3 SOFT. .. remain at the value determined by the last memory read Figure 3.2: Write operation Similarly, a read operation is started at the rising edge of CLKA signal The read enable control input and address input are latched at the beginning of each cycle The data output latch is latched following each read access, controlled by the track path Figure 3.3: Read operation 3.1.4.2 Built -in EDC operation In each... clock input CENB Write enable CENA Read enable AA Read address AB Write address DI Data in QO Data output RAM_MODE EDC block disable pin · RAM_MODE = 0: the SRAM will work with error detecting and correcting tasks · RAM_MODE = 1: the SRAM will work in normal mode, without error detecting and correcting tasks DE Double bit error flag SE Single bit error flag PE Parity bit error flag... each write operation, the 16 bit data input DI of EDC will be encoded to 6 parity bits following the Hamming code After that, 16 bit data input and 6 parity bits will propagate to 22-bit data in ports DB of the SRAM That means, in the memory array, only 16 bit is CHAPTER 3 SOFT ERROR TOLERANT SRAM DESIGN P a g e | 14 data information, the other 6 bits contain the error correcting code, which... during normal mode (read/write), it will not affect a lot the read and write performance The level of soft error tolerant depends a lot on the physical parameter and characteristic of the extra transistors Increasing width of extra transistor could enhance the tolerance level; however, this will trade off with the area overhead 3.2.2 Replica path for Read operation CHAPTER SOFT ERROR TOLERANT SRAM DESIGN. .. flag 3.1.4 Operation brief description 3.1.4.1 SRAM operation A write operation is started at the rising edge of CLKB signal The write enable control input, data input and address input are latched at the beginning of each cycle During a write operation, data will be written into the memory, and the data will not propagate to the memory output CHAPTER 3 SOFT ERROR TOLERANT SRAM DESIGN P a g e | 13 The... frequency is 200MHz (at worst case) · Hand-crafted layout · 22 bit data in/ out for SRAM · Only 16 bit data in/ out for EDC block interface because the remaining 6 bit data of SRAM were used as parity bit check · 8 row addresses input and 2 column addresses IO · Two independent clocks for read and write operations as well as two independent data in/ out ports and address buses · Some parts of the design were selected... CHAPTER 3 SOFT ERROR TOLERANT SRAM DESIGN 3.1 SRAM specification 3.1.1 General information · Two-ports synchronous SRAM 22kbit memory · Built -in Error Detecting and Correcting (EDC) block to mitigate soft error The EDC block could detect single bit/double bit error and only fix single bit error · This SRAM was designed in 130nm CMOS technology · Operating voltage range is from 1.35V to 1.65V · Operating... CHAPTER 1 INTRODUCTION Pag e |3 Chapter 3 describes detail about the SRAM design, including the SRAM specification, SRAM architecture, specific design for soft error tolerant feature and the physical implementation Chapter 4 focuses on the verification methodologies and the simulations result These simulations include the soft error tolerant level simulation, memory cell characteristic, post layout . a SRAM design with additional soft error tolerant feature will be presented. The SRAM is designed in 130nm CMOS technology, using circuit hardening and. release the alpha particles as well as other particles such as gamma and beta particles, as they decay to lower state. Alpha particles contain the kinetic