... Q_VitalGlitchData, Mode => DefGlitchMode, XOn => DefGlitchXOn); end process; end AltVITAL; configuration CFG_DFF _VITAL of DFF is for AltVITAL end for; end CFG_DFF _VITAL; 391 CPU :Vital Simulation ... HDL Capture RTL Simulation RTL Synthesis Functional Gate Simulation Place and Route Post Layout Timing Simulation Figure 17-1 High-Density Design Flow. 381 CPU :Vital Simulation VITAL Library One ... setup and hold check. VITAL Simulation To run the VITAL simulation, the designer first compiles the VITAL li- brary into a simulator library. The device manufacturers supply VITAL libraries for...