... not (s0,A); not (s1,B); not (s2,C); and (Q0,s0,s1,s2); and (Q1,A,s1,s2); and (Q2,s0,B,s2); and (Q3,A,B,s2); and (Q4,s0,s1,C); and (Q5,A,s1,C); and (Q6,s0,B,C); and (Q7,A,B,C); endmodule //*****TESTBENCH*******// ... Verilog program for AND gate: // And Gate (In Dataflow, behavioral Modeling): Module andg(a,b,c); input a,b; output c; assign c = a & b; endmodule //behavioural modeling Module andg1(a,b,c); input ... TECHNOLOGICAL UNIVERSITY HYDERABAD IV Year B.Tech ECE - I Sem L T/P/D C -/3/- E-CAD AND VLSI LAB List of Experiments Design and implementation of the following CMOS digital/analog circuits using Cadence...