... Asynchronous design, 23 0 bundled data, 23 0 dual-rail, 23 1 Asynchronous latch controller, 24 0 Body-bias, 2, 12, 20 adaptive, 4, 25 , 45, 77 controller, 88 forward, 27 , 60 reverse, 27 , 55 Canary ... (GIDL), 20 , 39 subthreshold, 2, 17, 50 Leakage current monitor, 56 Low-dropout (LDO), 109 Manufacturing test, 27 2, 27 9 ATPG, 28 0 clock de-skew, 28 8 power management, 28 9 wafer sort, 28 0 ... Narendra and Anantha Chandrakasan ISBN 9 78- 0- 387 -25 737 -2, 20 05 Statistical Analysis and Optimization for VLSI: Timing and Power Ashish Srivastava, Dennis Sylvester, and David Blaauw ISBN 9 78- 0- 387 -26 049-9,...