... Borkar N, Hamzaoglu F, Pandya G, Farhang A, Zhang K, De V (20 06) A 4.2GHz 0.3mm2 25 6kb Dual-Vcc SRAM Building Block in 65 nm CMOS. ISSCC Dig. Tech. Papers, pp 25 72 25 73 25 6 John J. Wuu basis ... matching P2 and P2’ FETs clamp SramVSS at A2. The resulting SramVSS is the lower of A1 and A2, producing Equation (11.1). Chapter 11 Dynamic and Adaptive Techniques in SRAM Design 25 5 In ... wafer probe to account for process variations. Figure 11.11 Active sleep control [10]. (â IEEE 20 06) Chapter 11 Dynamic and Adaptive Techniques in SRAM Design 26 5 For example, the “wake”...