... Motivating Adaptive Techniques 21
1.5 Conclusion
Variability and leakage are major technology challenges for both present
and future integrated circuits, and the adoption of adaptive techniques ... Bias Techniques for SH4,” Short Course on Physical
Design for Low Power, High Performance Microprocessor Circuits, 2001
Symposium on VLSI Circuits, 2001.
[17] D. Scott,...
... Experimental results have been obtained for both 90nm
and 65nm CMOS technology nodes.
A. Wang, S. Naffziger (eds.), Adaptive Techniques for Dynamic Processor Optimization,
DOI: 10.1007/978-0-387-76472-6_2, ... scaling and tuning for the 65nm LP-CMOS ringo.
Let us now investigate the frequency-scaling and tuning ranges offered
by AVS and ABB in 65nm LP-CMOS. For...
... informa-
tion, more sophisticated control is possible for further power reduction.
A. Wang, S. Naffziger (eds.), Adaptive Techniques for Dynamic Processor Optimization,
DOI: 10.1007/978-0-387-76472-6_3, ... both the active and the standby modes and raises V
TH
by 0.25V in the standby mode.
Chapter 2 Technological Boundaries of Voltage and Frequency Scaling 45...
... expected to last till the lifetime of
for Ultra -dynamic Voltage Scaled Systems
A. Wang, S. Naffziger (eds.), Adaptive Techniques for Dynamic Processor Optimization,
DOI: 10.1007/978-0-387-76472-6_5, ...
detect the droop and dynamically respond by lowering frequency. The
maximum frequency can then by increased by 32% for this large voltage
droop, improving aver...
...
[1] V. Gutnik and A. Chandrakasan, “Embedded power supply for low-power
DSP,” IEEE Trans. VLSI Syst., vol. 5, no. 4, pp. 425–435, Dec. 1997.
[2] A. Sinha and A. Chandrakasan, Dynamic power ... D. Blaauw, “Statistical analysis and optimization
for VLSI: timing and power,” New York, Springer, pp. 79–132, 2005.
Chapter 5 Adaptive Supply Voltage Delivery for U-DVS Systems 1...
... of this microarchitecture
performed by Herbert et al. [7].
in Multi-Clock Processors
A. Wang, S. Naffziger (eds.), Adaptive Techniques for Dynamic Processor Optimization,
DOI: 10.1007/978-0-387-76472-6_9, ... proposed by Butts
and Sohi [5] and complements Wattch’s dynamic power model. The model
uses estimates of the number of transistors (scaled by design-depend...
... completion and, in any case, ‘real’ additions do
not use purely random operands [13]. Nevertheless, a much cheaper unit
can supply respectable performance by adapting its timing to the oper-
ands ... constraints.
Simulations were completed for seven of the benchmarks: the 164.gzip,
175 .vpr, 197.parser, and 256.bzip2 integer benchmarks and the 177 .mesa,
183.equake, and 188.a...
... discussion of error correction and dynamic cache line
disable or reconfiguration options.
in SRAM Design
A. Wang, S. Naffziger (eds.), Adaptive Techniques for Dynamic Processor Optimization,
DOI: 10.1007/978-0-387-76472-6_11, ... designing stable SRAM cells that meet
product density and voltage requirements.
This chapter examines various dynamic and adaptive t...
...
Statistical Analysis and Optimization for VLSI: Timing and Power
Ashish Srivastava, Dennis Sylvester, and David Blaauw
ISBN 978-0-387-26049-9, 2005
Chapter 12 The Challenges of Testing Adaptive Designs ...
“Application and Analysis of RT-Level Software-Based Self-testing for
Embedded Processor Cores”, IEEE Intetrnational Test C440.
[17] Wei-Cheng Lai, Kwang-Ting Ch...