Adaptive Techniques for Dynamic Processor Optimization Theory and Practice by Alice Wang and Samuel Naffziger 9 pot

Adaptive Techniques for Dynamic Processor Optimization Theory and Practice by Alice Wang and Samuel Naffziger_2 doc

... Challenges Motivating Adaptive Techniques 19 Figure 1.18 The peak electric field is at the surface and influenced by the gate voltage. (© 2005 IEEE) [ 19] In Figure 1. 19, the potential profile ... Motivating Adaptive Techniques 21 1.5 Conclusion Variability and leakage are major technology challenges for both present and future integrated circuits, and the adoption of adaptive techniques ... 461–4 69, April 197 9. [ 19] S. Zhao, S. Tang, M. Nandakumar, D. B. Scott, S. Sridhar, A. Chatterjee, Y. Kim, S H. Yang, S C. Ai, and S. P. Ashburn, “GIDL Simulation and Opti-mization for 0.13um,...

Adaptive Techniques for Dynamic Processor Optimization Theory and Practice by Alice Wang and Samuel Naffziger_3 doc

... results have been obtained for both 90 nm and 65nm CMOS technology nodes. A. Wang, S. Naffziger (eds.), Adaptive Techniques for Dynamic Processor Optimization, DOI: 10.1007 /97 8-0-387-76472-6_2, © ... 250E+6275E+6300E+6325E+6350E+6375E+6400E+6425E+6450E+6000E+0 50E -9 100E -9 150E -9 200E -9 250E -9 300E -9 350E -9 400E -9 450E -9 CGU leakage current [A]Frequency [Hz]slowfasttypicalunbalancedCorner ... Voltage and Frequency Scaling 37 Table 2.3 Power–frequency-tuning ranges for 90 nm and 65nm CMOS. 90 nm GP 90 nm LP 65nm LP AVS Power savings + frequency penalty 13.7× 3.4× 23.6× 5 .9 82.0×...

Adaptive Techniques for Dynamic Processor Optimization Theory and Practice by Alice Wang and Samuel Naffziger_4 pptx

... sophisticated control is possible for further power reduction. A. Wang, S. Naffziger (eds.), Adaptive Techniques for Dynamic Processor Optimization, DOI: 10.1007 /97 8-0-387-76472-6_3, © Springer ... both the active and the standby modes and raises VTH by 0.25V in the standby mode. Chapter 2 Technological Boundaries of Voltage and Frequency Scaling 45 based on voltage and frequency ... pp. 888– 899 [12] T. Sakurai and R. Newton, “Alpha-power law MOSFET model and its applications to CMOS inverter delay and other formulas”, IEEE Journal of Solid-State Circuits, April 199 0, Vol....

Adaptive Techniques for Dynamic Processor Optimization Theory and Practice by Alice Wang and Samuel Naffziger_6 pdf

... last till the lifetime of for Ultra -dynamic Voltage Scaled Systems A. Wang, S. Naffziger (eds.), Adaptive Techniques for Dynamic Processor Optimization, DOI: 10.1007 /97 8-0-387-76472-6_5, © Springer ... detect the droop and dynamically respond by lowering frequency. The maximum frequency can then by increased by 32% for this large voltage droop, improving average performance for the workload. ... Nair, D. Antoniadis, A. Chandrakasan, and V. De, Adaptive body bias for reducing impacts of die-to-die and within-die parameter variations on microprocessor frequency and leakage”, IEEE J. Solid-State...

Adaptive Techniques for Dynamic Processor Optimization Theory and Practice by Alice Wang and Samuel Naffziger_7 potx

... [1] V. Gutnik and A. Chandrakasan, “Embedded power supply for low-power DSP,” IEEE Trans. VLSI Syst., vol. 5, no. 4, pp. 425–435, Dec. 199 7. [2] A. Sinha and A. Chandrakasan, Dynamic power ... and Design, pp. 76–81, 199 8. [20] B. H. Calhoun and A. P. Chandrakasan, “Ultra -dynamic voltage scaling us-ing sub-threshold operation and local voltage dithering in 90 nm CMOS,” IEEE ISSCC ... J. Duinmaijer, and A. P. G. Welbers, “Matching properties of MOS transistors,” IEEE J. Solid-State Circuits, vol. 24, no. 5, pp. 1433–14 39, Oct. 198 9. [9] J. Kwong, A. P. Chandrakasan, “Variation-driven...

Adaptive Techniques for Dynamic Processor Optimization Theory and Practice by Alice Wang and Samuel Naffziger_9 pot

... defined, the microprocessor passes through logic, A. Wang, S. Naffziger (eds.), Adaptive Techniques for Dynamic Processor Optimization, DOI: 10.1007 /97 8-0-387-76472-6_7, © Springer Science+Business ... essentially an FET wire; and NAND and NOR gate paths consisting of a series of 4-high NAND and 3-high NOR gates respectively. Simulations were performed at two frequencies, F and F/3 where F was ... the performance of the microprocessor, even when within-die variation is significant, adding a de-sign margin and binning is sufficient for determining the performance of the microprocessor...

Adaptive Techniques for Dynamic Processor Optimization Theory and Practice by Alice Wang and Samuel Naffziger_12 ppt

... microarchitecture performed by Herbert et al. [7]. in Multi-Clock Processors A. Wang, S. Naffziger (eds.), Adaptive Techniques for Dynamic Processor Optimization, DOI: 10.1007 /97 8-0-387-76472-6 _9, © Springer ... James and M. Floyd, “A distributed critical-path timing monitor for a 65nm high-performance microprocessor,” International Solid-State Circuits Conference, pp. 398 – 399 , 2007. Chapter 9 Variability-Aware ... January. 2005 [ 19] T. Kehl, “Hardware self-tuning and circuit performance monitoring,” 199 3 Int’l Conference on Computer Design (ICCD -93 ), October 199 3. [20] S. Lu, “Speeding up processing with...

Adaptive Techniques for Dynamic Processor Optimization Theory and Practice by Alice Wang and Samuel Naffziger_13 pdf

... M. Orshansky, C. Spanos and C. Hu, “Circuit Performance Variability Decomposition”, IWSM 99 : Proceedings of the 4th International Workshop on Statistical Metrology, 199 9, pp. 10–13 [14] G. Semeraro, ... completion and, in any case, ‘real’ additions do not use purely random operands [13]. Nevertheless, a much cheaper unit can supply respectable performance by adapting its timing to the oper-ands ... completed for seven of the benchmarks: the 164.gzip, 175.vpr, 197 .parser, and 256.bzip2 integer benchmarks and the 177.mesa, 183.equake, and 188.ammp floating point benchmarks. 9. 5 Results...

Adaptive Techniques for Dynamic Processor Optimization Theory and Practice by Alice Wang and Samuel Naffziger_14 pptx

... correction and dynamic cache line disable or reconfiguration options. in SRAM Design A. Wang, S. Naffziger (eds.), Adaptive Techniques for Dynamic Processor Optimization, DOI: 10.1007 /97 8-0-387-76472-6_11, ... Controllers for Low Power Asynchronous Circuits”, Proceedings of Async&apos ;99 , IEEE Computer Society Press, April 199 9, pp. 27–35. [18] A. Efthymiou, “Asynchronous Techniques for Power -Adaptive ... J.D. Garside and D.A. Gilbert, “AMULET3: A High-Performance Self-Timed ARM Microprocessor”, Proceedings of ICCD&apos ;98 , Austin, TX, 5–7 October 199 8, pp. 247–252. ISBN 0-8186 -90 99- 2. [6] S.B....

Adaptive Techniques for Dynamic Processor Optimization Theory and Practice by Alice Wang and Samuel Naffziger_17 pot

... Chandrakasan ISBN 97 8-0-387-25737-2, 2005 Statistical Analysis and Optimization for VLSI: Timing and Power Ashish Srivastava, Dennis Sylvester, and David Blaauw ISBN 97 8-0-387-260 49- 9, 2005 Chapter ... Refinement for Large Scale Model Checking Chao Wang, Gary D. Hachtel, and Fabio Somenzi ISBN 97 8-0-387-28 594 -2, 2006 A Practical Introduction to PSL Cindy Eisner and Dana Fisman ISBN 97 8-0-387-35313-5, ... 12 The Challenges of Testing Adaptive Designs 299 From a manufacturability standpoint, both analog and architectural designs require similarly sized guard-bands (Adaptive Op. Point, Figure 12.18)...

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